AGL600V2-FGG484 Actel, AGL600V2-FGG484 Datasheet - Page 130

• Manufacturer Part Number: AGL600V2-FGG484
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AGL600V2-FGG484

• Processor Series: AGL600
• Core: IP Core
• Maximum Operating Frequency: 526.32 MHz, 892.86 MHz
• Number Of Programmable I/os: 235
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 600 K
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IGLOO DC and Switching Characteristics
Table 2-189 • IGLOO CCC/PLL Specification
2- 11 6
Parameter
Clock Conditioning Circuitry Input Frequency f
Clock Conditioning Circuitry Output Frequency f
Delay Increments in Programmable Delay Blocks
Number of Programmable Values in Each Programmable Delay Block
Serial Clock (SCLK) for Dynamic PLL
Input Cycle-to-Cycle Jitter (peak magnitude)
CCC Output Peak-to-Peak Period Jitter F
Acquisition Time
Tracking Jitter
Output Duty Cycle
Delay Range in Block: Programmable Delay 1
Delay Range in Block: Programmable Delay 2
Delay Range in Block: Fixed Delay
Notes:
1. This delay is a function of voltage and temperature. See
2. T
3. Maximum value obtained for a Std. speed grade device in Worst-Case Commercial Conditions. For specific junction
4. For the definitions of Type 1 and Type 2, refer to the PLL Block Diagram in the Clock Conditioning Circuits in IGLOO and
5. The AGL030 device does not support PLL.
6. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock
temperature and voltage supply levels, refer to
ProASIC3 Devices chapter of the
edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter
parameter.
0.75 MHz to 24 MHz
24 MHz to 100 MHz
100 MHz to 160 MHz
J
= 25°C, V
For IGLOO V2 Devices, 1.2 V DC Core Supply Voltage
CC
= 1.5 V
1, 2, 4
IGLOO FPGA Fabric User’s
3
CCC_OUT
IN_CCC
1, 2, 4
1, 2, 4
OUT_CCC
Table 2-6 on page 2-7
1, 2
LockControl = 0
LockControl = 1
LockControl = 0
LockControl = 1
R ev isio n 1 8
Table 2-6 on page 2-7
Guide.
for derating values.
1 Global
Network
0.50%
1.00%
2.50%
0.863
Used
Min.
0.75
Maximum Peak-to-Peak Period Jitter
48.5
2.3
1.5
and
Table 2-7 on page 2-7
FB Used
External
0.75%
1.50%
3.75%
Typ.
580
5.7
Networks
3 Global
0.70%
1.20%
2.75%
20.86
20.86
Used
Max.
0.25
160
160
300
51.5
6.0
60
32
4
3
for deratings.
Units
MHz
MHz
ms
ps
ns
ns
µs
ns
ns
ns
ns
ns
%