LFE3-150EA-7FN672CTW Lattice, LFE3-150EA-7FN672CTW Datasheet - Page 8
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LFE3-150EA-7FN672CTW
Manufacturer Part Number
LFE3-150EA-7FN672CTW
Description
FPGA - Field Programmable Gate Array 149K LUTs 380 I/O 1.2V -7 Speed
Manufacturer
Lattice
Datasheet
1.LFE3-150EA-7FN672CTW.pdf
(130 pages)
Specifications of LFE3-150EA-7FN672CTW
Number Of Programmable I/os
133 to 586
Data Ram Size
6.85 Mbits
Delay Time
37 ns
Supply Voltage (max)
1.26 V
Supply Current
18 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-672
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE3-150EA-7FN672CTW
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
Modes of Operation
Each slice has up to four potential modes of operation: Logic, Ripple, RAM and ROM.
Logic Mode
In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16
possible input combinations. Any four input logic functions can be generated by programming this lookup table.
Since there are two LUT4s per slice, a LUT5 can be constructed within one slice. Larger look-up tables such as
LUT6, LUT7 and LUT8 can be constructed by concatenating other slices. Note LUT8 requires more than four
slices.
Ripple Mode
Ripple mode supports the efficient implementation of small arithmetic functions. In ripple mode, the following func-
tions can be implemented by each slice:
Ripple Mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this con-
figuration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are gener-
ated on a per slice basis to allow fast arithmetic functions to be constructed by concatenating Slices.
RAM Mode
In this mode, a 16x4-bit distributed single port RAM (SPR) can be constructed using each LUT block in Slice 0 and
Slice 1 as a 16x1-bit memory. Slice 2 is used to provide memory address and control signals. A 16x2-bit pseudo
dual port RAM (PDPR) memory is created by using one Slice as the read-write port and the other companion slice
as the read-only port.
LatticeECP3 devices support distributed memory initialization.
The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft-
ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3
shows the number of slices required to implement different distributed RAM primitives. For more information about
using RAM in LatticeECP3 devices, please see TN1179,
Table 2-3. Number of Slices Required to Implement Distributed RAM
• Addition 2-bit
• Subtraction 2-bit
• Add/Subtract 2-bit using dynamic control
• Up counter 2-bit
• Down counter 2-bit
• Up/Down counter with asynchronous clear
• Up/Down counter with preload (sync)
• Ripple mode multiplier building block
• Multiplier support
• Comparator functions of A and B inputs
– A greater-than-or-equal-to B
– A not-equal-to B
– A less-than-or-equal-to B
Number of slices
Note: SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM
SPR 16X4
2-5
LatticeECP3 Memory Usage
3
LatticeECP3 Family Data Sheet
PDPR 16X4
Guide.
3
Architecture