A42MX09-PLG84 Actel, A42MX09-PLG84 Datasheet - Page 19
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A42MX09-PLG84
Manufacturer Part Number
A42MX09-PLG84
Description
FPGA - Field Programmable Gate Array 14K System Gates
Manufacturer
Actel
Datasheet
1.A40MX04-PLG44.pdf
(124 pages)
Specifications of A42MX09-PLG84
Processor Series
A42MX09
Core
IP Core
Number Of Macrocells
336
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
104
Delay Time
5.6 ns
Supply Voltage (max)
5.5 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
3 V
Number Of Gates
14 K
Package / Case
PLCC-84
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A42MX09-PLG84
Manufacturer:
MICROSEMI/美高森美
Quantity:
20 000
Company:
Part Number:
A42MX09-PLG84A
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
A42MX09-PLG84I
Manufacturer:
NXP
Quantity:
12 000
Company:
Part Number:
A42MX09-PLG84I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Development Tool Support
The MX family of FPGAs is fully supported by both Actel's
Libero™ Integrated Design Environment and Designer
FPGA Development software. Actel Libero IDE is a design
management environment that streamlines the design
flow. Libero IDE provides an integrated design manager
that seamlessly integrates design tools while guiding the
user through the design flow, managing all design and
log files, and passing necessary design data among tools.
Additionally, Libero IDE allows users to integrate both
schematic and HDL synthesis into a single flow and verify
the entire design in a single environment. Libero IDE
includes Synplify® for Actel from Synplicity®, ViewDraw
for Actel from Mentor Graphics, ModelSim™ HDL
Simulator from Mentor Graphics®, WaveFormer Lite™
from SynaptiCAD™, and Designer software from Actel.
Refer to the
diagram for more information.
Actel's Designer software is a place-and-route tool and
provides a comprehensive suite of backend support tools
for FPGA development. The Designer software includes
timing-driven
integrated static timing analyzer and constraints editor.
With the Designer software, a user can lock his/her
design pins before layout while minimally impacting the
results of place-and-route. Additionally, the back-
annotation flow is compatible with all the major
simulators and the simulation results can be cross-probed
with Silicon Explorer II, Actel’s integrated verification
and logic analysis tool. Another tool included in the
Designer software is the ACTgen macro builder, which
easily creates popular and commonly used logic
functions for implementation into your schematic or HDL
design. Actel's Designer software is compatible with the
most popular FPGA design entry and verification tools
from companies such as Mentor Graphics, Synplicity,
Synopsys, and Cadence Design Systems. The Designer
software is available for both the Windows and UNIX
operating systems.
Actel's Designer software is compatible with the most
popular FPGA design entry and verification tools from
companies such as Mentor Graphics, Synplicity, Synopsys,
and Cadence Design Systems. The Designer software is
available for both the Windows and UNIX operating
systems.
Libero IDE flow
place-and-route,
(located on Actel’s website)
and
a
world-class
v6.1
Related Documents
Application Notes
Actel BSDL Files Format Description
www.actel.com/documents/BSDLformat_AN.pdf
Programming Antifuse Devices
http://www.actel.com/documents/
AntifuseProgram_AN.pdf
Actel's Implementation of Security in Actel Antifuse
FPGAs
www.actel.com/documents/Antifuse_Security_AN.pdf
User’s Guides and Manuals
Antifuse Macro Library Guide
www.actel.com/documents/libguide_UG.pdf
Silicon Sculptor II
www.actel.com/techdocs/manuals/default.asp#programmers
Miscellaneous
Libero IDE Flow Diagram
www.actel.com/products/tools/libero/flow.html
40MX and 42MX FPGA Families
1-13