A42MX16-PLG84 Actel, A42MX16-PLG84 Datasheet - Page 76

• Manufacturer Part Number: A42MX16-PLG84
• Description: FPGA - Field Programmable Gate Array 24K System Gates
• Manufacturer: Actel

Specifications of A42MX16-PLG84

• Processor Series: A42MX16
• Core: IP Core
• Number Of Macrocells: 608
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 140
• Delay Time: 5.6 ns
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 3 V
• Number Of Gates: 24 K
• Package / Case: PLCC-84
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 38 •
1 -7 0
Parameter Description
Synchronous SRAM Operations (Continued)
t
t
t
t
t
t
t
Asynchronous SRAM Operations
t
t
t
t
t
t
t
t
t
Input Module Propagation Delays
t
t
t
t
t
Notes:
1. For dual-module macros, use t
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
5. Delays based on 35 pF loading.
ADH
RENSU
RENH
WENSU
WENH
BENS
BENH
RPD
RDADV
ADSU
ADH
RENSUA
RENHA
WENSU
WENH
DOH
INPY
INGO
INH
INSU
ILA
40MX and 42MX FPGA Families
device performance. Post-route timing analysis or simulation is required to determine actual performance.
obtained from the Timer utility.
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
A42MX36 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, V
Address/Data Hold Time
Read Enable Set-Up
Read Enable Hold
Write Enable Set-Up
Write Enable Hold
Block Enable Set-Up
Block Enable Hold
Asynchronous Access Time
Read Address Valid
Address/Data Set-Up Time
Address/Data Hold Time
Read Enable Set-Up to Address
Valid
Read Enable Hold
Write Enable Set-Up
Write Enable Hold
Data Out Hold Time
Input Data Pad-to-Y
Input Latch Gate-to-Output
Input Latch Hold
Input Latch Set-Up
Latch Active Pulse Width
PD1
+ t
RD1
+ t
PDn
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
‘–3’ Speed
0.0
0.6
3.4
2.7
0.0
2.8
0.0
8.8
1.6
0.0
0.6
3.4
2.7
0.0
0.0
0.5
4.7
, t
CO
CCA
+ t
8.1
1.2
1.0
1.4
RD1
= 4.75V, T
+ t
v6.1
‘–2’ Speed
PDn
0.0
0.7
3.8
3.0
0.0
3.1
0.0
9.8
1.8
0.0
0.7
3.8
3.0
0.0
0.0
0.5
5.2
, or t
J
= 70°C)
9.0
PD1
1.3
1.1
1.6
+ t
RD1
11.1
‘–1’ Speed
0.0
0.8
4.3
3.4
0.0
3.5
0.0
2.0
0.0
0.8
4.3
3.4
0.0
0.0
0.6
5.9
+ t
SUD
10.2
1.5
1.3
1.8
, whichever is appropriate.
‘Std’ Speed
13.0
0.0
0.9
5.0
4.0
0.0
4.1
0.0
2.4
0.0
0.9
5.0
4.0
0.0
0.0
0.7
6.9
12.0
1.8
1.5
2.1
18.2
‘–F’ Speed
1.3
5.6
5.6
0.0
7.0
0.0
5.7
0.0
3.4
0.0
1.3
7.0
0.0
0.0
1.0
9.7
16.8
2.5
2.1
2.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns