LFX125EB-04FN256C Lattice, LFX125EB-04FN256C Datasheet - Page 57
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFX125EB-04FN256C
Manufacturer Part Number
LFX125EB-04FN256C
Description
FPGA - Field Programmable Gate Array E-Ser139K Gt ispJTAG 2.5/3.3V -4 Spd
Manufacturer
Lattice
Specifications of LFX125EB-04FN256C
Number Of Macrocells
1936
Number Of Programmable I/os
160
Data Ram Size
94208
Supply Voltage (max)
3.6 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.65 V
Number Of Gates
139 K
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFX125EB-04FN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
sysCLOCK PLL Timing
t
t
t
t
f
f
f
f
f
f
t
t
t
t
t
t
t
t
t
t
t
1. This condition assures that the output phase jitter will remain within specifications. Jitter spec is based on optimized M, N and V settings
2. Accumulated jitter measured over 10,000 waveform samples
3. Internal timing for reference only.
PWH
PWL
R
INSTB
MDIVIN
MDIVOUT
NDIVIN
NDIVOUT
VDIVIN
VDIVOUT
OUTDUTY
JIT(CC)
JIT(PER)
CLK_OUT_DELAY
PHASE
LOCK
PLL_DELAY
RANGE
PLL_RSTW
CLK_IN
PLL_SEC_DELAY
, t
determined by the ispLEVER software.
F
Symbol
3
2
Input clock, high time
Input clock, low time
Input Clock, rise and fall time
Input clock stability, cycle to cycle (peak)
M Divider input, frequency range
M Divider output, frequency range
N Divider input, frequency range
N Divider output, frequency range
V Divider input, frequency range
V Divider output, frequency range
output clock, duty cycle
Output clock, cycle to cycle jitter (peak)
Output clock, period jitter (peak)
Input clock to CLK_OUT delay
Input clock to external feedback delta
Time to acquire phase lock after input stable
Delay increment (Lead/Lag)
Total output delay range (lead/lag)
Minimum reset pulse width
Global clock input delay
Secondary PLL output delay
Parameter
Over Recommended Operating Conditions
57
80% to 80%
20% to 20%
20% to 80%
Clean reference
10MHz ≤ f
100MHz ≤ f
Clean reference
40MHz ≤ f
160MHz ≤ f
Clean reference
10MHz ≤ f
100MHz ≤ f
Clean reference
40MHz ≤ f
160MHz ≤ f
Internal feedback
External feedback
Typical = +/- 250ps
MDIVOUT
MDIVOUT
MDIVOUT
MDIVOUT
VDIVIN
VDIVIN
VDIVIN
Conditions
VDIVIN
1
1
1
1
≤ 400MHz
≤ 160MHz
≤ 400MHz
≤ 160MHz
≤ 40MHz or
≤ 320MHz and
≤ 40MHz or
≤ 320MHz and
ispXPGA Family Data Sheet
+/- 0.84 +/- 3.85
+/- 120 +/- 550
Min
100
1.2
1.2
1.8
10
10
10
10
10
40
—
—
—
—
—
—
—
—
—
—
—
+/- 250
+/- 600
+/- 150
+/- 600
+/- 150
Max
320
320
320
320
400
320
3.0
3.0
1.5
1.0
1.5
60
25
—
—
—
Units
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ps
ps
ps
ps
ps
ns
ns
us
ps
ns
ns
ns
ns
%