LFSC3GA25E-7FN900C Lattice, LFSC3GA25E-7FN900C Datasheet - Page 36

• Manufacturer Part Number: LFSC3GA25E-7FN900C
• Description: FPGA - Field Programmable Gate Array 25.4K LUTs 378 3G SERDES 1.2V -7 Spd
• Manufacturer: Lattice

Specifications of LFSC3GA25E-7FN900C

• Number Of Macrocells: 25000
• Number Of Programmable I/os: 132 to 942
• Data Ram Size: 1916928
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 0.95 V
• Package / Case: FPBGA-900
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Differential Input Termination
The LatticeSC device allows two types of differential termination. The first is a single resistor across the differential
inputs. The second is a center-tapped system where each input is terminated to the on-chip termination bus V
The V
Figure 2-29 shows the differential termination schemes and Table 2-9 shows the nominal values of the termination
resistors.
Figure 2-29. Differential Termination Scheme
Calibration
There are two calibration sources that are associated with the termination scheme used in the LatticeSC devices:
The LatticeSC devices support two modes of calibration:
For more information on calibration, refer to the details of additional technical documentation at the end of this data
sheet.
Hot Socketing
The LatticeSC devices have been carefully designed to ensure predictable behavior during power-up and power-
down. To ensure proper power sequencing, care must be taken during power-up and power-down as described
below. During power-up and power-down sequences, the I/Os remain in tristate until the power supply voltage is
high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled to within specified limits,
Differential termination
Differential and common
mode termination
Termination Type
• DIFFR – This pin occurs in each bank that supports differential drivers and must be connected through a
• XRES – There is one of these pins per device. It is used for several functions including calibrating on-chip
• Continuous – In this mode the SC devices continually calibrate the termination resistances. Calibration hap-
• User Request – In this mode the calibration circuit operates continuously. However, the termination resistor
CMT
1K+/-1% resistor to ground if differential outputs are used. Note that differential drivers are not supported in
banks 1, 4 and 5.
termination. This pin should always be connected through a 1K+/-1% resistor to ground.
pens several times a second. Using this mode ensures that termination resistances remain calibrated as
the silicon junction temperature changes.
values are only updated on the assertion of the calibration_update signal available to the core logic.
bus is DC-coupled through an internal capacitor to ground.
GND
Zo
Zo
Zo
Zo
Discrete Off-Chip Solution
OFF-chip
OFF-chip
2Zo
Zo
Zo
ON-chip
ON-chip
2-32
+
+
-
-
LatticeSC/M Family Data Sheet
Zo
Zo
Zo
Zo
OFF-chip
Lattice On-Chip Solution
OFF-chip
VCMT
GND
ON-chip
ON-chip
Zo
Zo
2Zo
Architecture
+
-
+
-
CMT
.