SRV05-4A.TCT Semtech, SRV05-4A.TCT Datasheet - Page 8

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SRV05-4A.TCT

Manufacturer Part Number
SRV05-4A.TCT
Description
TVS
Manufacturer
Semtech
Datasheet

Specifications of SRV05-4A.TCT

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
SRV05-4ATR
DVI Protection
The small geometry of a typical digital-visual interface
(DVI) graphic chip will make it more susceptible to
electrostatic discharges (ESD) and cable discharge
events (CDE). Transient protection of a DVI port can
be challenging. Digital-visual interfaces can often
transmit and receive at a rate equal to or above
1Gbps. The high-speed data transmission requires the
protection device to have low capacitance to maintain
signal integrity and low clamping voltage to reduce
stress on the protected IC. The SRV05-4A has a low
typical insertion loss of <0.4dB at 1GHz (I/O to ground)
to ensure signal integrity and can protect the DVI
interface to the 8kV contact and 15kV air ESD per IEC
61000-4-2 and CDE.
Figure 7 shows how to design the SRV05-4A into the
DVI circuit on a flat panel display and a PC graphic
card. The SRV05-4A is configured to provide common
mode and differential mode protection. The internal
TVS of the SRV05-4A acts as a 5 volt reference. The
power pin of the DVI circuit does not come out through
the connector and is not subjected to external ESD
pulse; therefore, pin 5 should be left unconnected.
Connecting pin 5 to Vcc of the DVI circuit may result in
damage to the chip from ESD current.
PROTECTION PRODUCTS
© 2010 Semtech Corp.
Figure 7 - Digital Visual Interface (DVI) Protection
8
10/100 ETHERNET PROTECTION
Ethernet ICs are vulnerable to damage from electro-
static discharge (ESD).
PHY chip, if any, often is not enough due to the high
energy of the discharges specified by IEC 61000-4-2.
If the discharge is catastrophic, it will destroy the
protected IC. If it is less severe, it will cause latent
failures that are very difficult to find.
In a typical 10/100 system, the twisted-pair interface
for each port consists of two differential signal pairs:
one for the transmitter and one for the receiver, with
the transmitter input being the most sensitive to
damage. The fatal discharge occurs differentially
across the transmit or receive line pair and is capaci-
tively coupled through the transformer to the Ethernet
chip. Figure 8 shows how to design the SRV05-4A on
the line side of a 10/100 ethernet port to provide
differential mode protection. The common mode
isolation of the transformer will provide common mode
protection to the rating of the transformer isolation
which is usually >1.5kV. Figure 9 shows how to
implement the SRV05-4A on the IC side of the 10/
100 Ethernet circuit.
The internal protection in the
SRV05-4A
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