SI5321-H-BL Silicon Laboratories Inc, SI5321-H-BL Datasheet - Page 25

• Manufacturer Part Number: SI5321-H-BL
• Description: IC CLOCK MULT SONET/SDH 63-PBGA
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5321-H-BL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

*Note: The LVTTL inputs on the Si5321 device have an internal pulldown mechanism that causes the input to default to a
Pin #
D1
E1
G1
H1
H6
H7
F1
logic low state if the input is not driven from an external source.
INFRQSEL[0]
INFRQSEL[1]
INFRQSEL[2]
CLKOUT+
Pin Name
CLKOUT–
CLKIN+
CLKIN–
I/O
O
I*
I
Table 10. Si5321 Pin Descriptions
200–500 mV
(See Table 2)
Signal Level
AC Coupled
LVTTL*
CML
Rev. 2.5
PPD
System Clock Input.
Clock input to the DSPLL circuitry. The frequency of
the CLKIN signal is multiplied by the DSPLL to gen-
erate the CLKOUT clock output. The input-to-output
frequency multiplication factor is set by selecting the
clock input range and the clock output range. The
frequency of the CLKIN clock input can be in the 19,
38, 77, 155, 311, or 622 MHz range (nominally
19.44, 38.88, 77.76, 155.52, 311.04, or
622.08 MHz) as indicated in Table 3 on page 7. The
clock input frequency is selected using the INFRQ-
SEL[2:0] pins. The clock output frequency is
selected using the FRQSEL[1:0] pins. An additional
scaling factor may be selected for FEC operation
using the FEC[2:0] control pins.
Input Frequency Range Select.
Pins(INFRQSEL[2:0]) select the frequency range for
the input clock, CLKIN. (See Table 3 on page 7.)
000 = Reserved.
001 = 19 MHz range.
010 = 38 MHz range.
011 = 77 MHz range.
100 = 155 MHz range.
101 = 311 MHz range.
110 = 622 MHz range.
111 = Reserved.
Differential Clock Output.
High-frequency clock output. The frequency of the
CLKOUT output is a multiple of the frequency of the
CLKIN input. The input-to-output frequency multipli-
cation factor is set by selecting the clock input range
and the clock output range. The frequency of the
CLKOUT clock output can be in the 19, 38, 77, 155,
311, 622, 1244 or 2488 MHz range as indicated in
Table 3 on page 7. The clock output frequency is
selected using the FRQSEL[2:0] pins. The clock
input frequency is selected using the INFRQ-
SEL[2:0] pins. An additional scaling factor may be
selected for FEC operation using the FEC[2:0] con-
trol pins.
Description
Si5321
25