RX-4801JE:UB Epson Toyocom Corporation, RX-4801JE:UB Datasheet - Page 21

• Manufacturer Part Number: RX-4801JE:UB
• Description: REAL TIME CLOCK MODULE
• Manufacturer: Epson Toyocom Corporation

Specifications of RX-4801JE:UB

• Memory Size: *
• Time Format: *
• Date Format: *
• Interface: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5730413A

RX - 4801 SA / JE
8.4.2. Related registers for time update interrupt functions.
∗ )
∗ Before entering settings for operations, we recommend writing a "0" to the UIE bit to prevent hardware interrupts
∗ When the RESET bit value is "1" time update interrupt events do not occur.
∗ Although the time update interrupt function cannot be fully stopped, if "0" is written to the UIE bit, the time update
1) USEL (Update Interrupt Select) bit
2) UF (Update Flag) bit
3) UIE (Update Interrupt Enable) bit
Address
from occurring inadvertently while entering settings.
interrupt function can be prevented from changing the /INT pin status to low.
This bit is used to select "second" update or "minute" update as the timing for generation of time update interrupt
events.
Once it has been set to "0", this flag bit value changes from "0" to "1" when a time update interrupt event occurs.
When this flag bit = "1" its value is retained until a "0" is written to it.
When a time update interrupt event occurs (UF bit value changes from "0" to "1"), this bit selects whether to
generate an interrupt signal (/INT status changes from Hi-Z to low) or to not generate it (/INT status remains
Hi-Z).
"o" indicates write-protected bits. A zero is always read from these bits.
D
E
F
Write/Read
Write/Read
USEL
Write
Read
UIE
UF
Extension Register
Control Register
Flag Register
Function
Data
Data
Data
0
1
0
1
0
1
0
1
Selects "second update" (once per second) as the timing for generation of
interrupt events
Selects "minute update" (once per minute) as the timing for generation of
interrupt events
The UF bit is cleared to zero to prepare for the next status detection
∗
This bit is invalid after a "1" has been written to it.
Time update interrupt events are not detected.
Time update interrupt events are detected.
(The result is retained until this bit is cleared to zero.)
1) Does not generate an interrupt signal when a time update interrupt event
occurs (/INT remains Hi-Z)
2) Cancels interrupt signal triggered by time update interrupt event (/INT
changes from low to Hi-Z).
When a time update interrupt event occurs, an interrupt signal is generated
(/INT status changes from Hi-Z to low).
∗
∗
CSEL1
bit 7
TEST
Clearing this bit to zero does not enable the /INT low output status to be cleared (to Hi-Z).
Even when the UIE bit value is "0" another interrupt event may change the /INT status to low (or
may hold /INT = "L").
When a time update interrupt event occurs, low-level output from the /INT pin occurs only when
the UIE bit value is "1". Up to 7.8 ms after the interrupt occurs, the /INT status is automatically
cleared (/INT status changes from low to Hi-Z).
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CSEL0
WADA
bit 6
USEL
bit 5
UIE
UF
bit 4
TIE
TE
TF
Description
Description
Description
FSEL1
bit 3
AIE
AF
FSEL0
bit 2
TSEL1
bit 1
VLF
ETM27E-04
RESET
TSEL0
VDET
bit 0