PIC16LF721-I/SS Microchip Technology, PIC16LF721-I/SS Datasheet - Page 129
![MCU PIC 4K FLASH 20-SSOP](/photos/19/6/190623/4696163_sml.jpg)
PIC16LF721-I/SS
Manufacturer Part Number
PIC16LF721-I/SS
Description
MCU PIC 4K FLASH 20-SSOP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Specifications of PIC16LF721-I/SS
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
17
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP (0.200", 5.30mm Width)
Controller Family/series
PIC16LF
No. Of I/o's
18
Ram Memory Size
256Byte
Cpu Speed
16MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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16.2
The Baud Rate Generator (BRG) is an 8-bit timer that
is dedicated to the support of both the asynchronous
and synchronous AUSART operation.
The SPBRG register determines the period of the free
running baud rate timer. In Asynchronous mode the
multiplier of the baud rate period is determined by the
BRGH bit of the TXSTA register. In Synchronous mode,
the BRGH bit is ignored.
Table 16-3
baud rate.
for determining the baud rate and baud rate error.
Typical baud rates and error values for various
asynchronous modes have been computed for your
convenience and are shown in
advantageous to use the high baud rate (BRGH = 1), to
reduce the baud rate error.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures that
the BRG does not wait for a timer overflow before
outputting the new baud rate.
TABLE 16-3:
TABLE 16-4:
2010 Microchip Technology Inc.
Legend:
RCSTA
SPBRG
TXSTA
Legend:
Name
SYNC
0
0
1
AUSART Baud Rate Generator
(BRG)
Configuration Bits
Example 16-1
contains the formulas for determining the
x = Don’t care, n = value of SPBRG register
x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for the Baud Rate Generator.
CSRC
SPEN
BRG7
Bit 7
BAUD RATE FORMULAS
REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
BRG6
Bit 6
BRGH
RX9
TX9
provides a sample calculation
0
1
x
Table
SREN
BRG5
TXEN
Bit 5
16-5. It may be
CREN
BRG4
SYNC
Bit 4
AUSART Mode
Asynchronous
Asynchronous
Synchronous
ADDEN
BRG3
Bit 3
—
BRGH
FERR
BRG2
EXAMPLE 16-1:
Bit 2
For a device with F
9600, and Asynchronous mode with SYNC = 0 and BRGH
= 0 (as seen in
Solving for SPBRG:
%
Desired Baud Rate
Error
Actual Baud Rate
PIC16F/LF720/721
OERR
BRG1
TRMT
Bit 1
=
=
SPBRG
Actual Baud Rate Desired Baud Rate
------------------------------------------------------------------------------------------------- -
9615 9600
----------------------------- -
Table
9600
OSC
–
BRG0
RX9D
TX9D
Bit 0
16-5):
=
=
=
=
=
=
CALCULATING BAUD
RATE ERROR
Desired Baud Rate
-------------------------- -
64 25
9615
of 16 MHz, desired baud rate of
-------------------------------------- -
64 SPBRG
16000000
25.042
-------------------------------------------------------- -
64 Desired Baud Rate
----------------------- -
64
16000000
Baud Rate Formula
100
F
F
F
F
9600
OSC
OSC
0000 000x
0000 0000
0000 -010
OSC
+
POR, BOR
OS C
Value on
=
–
1
/[64 (n+1)]
/[16 (n+1)]
=
F
/[4 (n+1)]
0.16%
+
OS C
25
–
1
DS41430A-page 129
1
0000 000x
0000 0000
0000 -010
Value on
all other
Resets
–
1
100
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