PIC18LF25K80-I/SP Microchip Technology, PIC18LF25K80-I/SP Datasheet - Page 114
![MCU PIC 32KB FLASH 28SDIP](/photos/18/99/189989/4243185_sml.jpg)
PIC18LF25K80-I/SP
Manufacturer Part Number
PIC18LF25K80-I/SP
Description
MCU PIC 32KB FLASH 28SDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18LF25K80-I/SP
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Core Processor
PIC
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
Ram Memory Size
4KB
Cpu Speed
16MIPS
No. Of Pwm Channels
5
Embedded Interface Type
I2C, SPI, USART
Processor Series
PIC18LF25K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18F66K80 FAMILY
FIGURE 6-7:
6.3.2
While the use of the BSR, with an embedded 8-bit
address, allows users to address the entire range of data
memory, it also means that the user must ensure that the
correct bank is selected. If not, data may be read from,
or written to, the wrong location. This can be disastrous
if a GPR is the intended target of an operation, but an
SFR is written to instead. Verifying and/or changing the
BSR for each read or write to data memory can become
very inefficient.
To streamline access for the most commonly used data
memory locations, the data memory is configured with
an Access Bank, which allows users to access a
mapped block of memory without specifying a BSR.
The Access Bank consists of the first 96 bytes of
memory (00h-5Fh) in Bank 0 and the last 160 bytes of
memory (60h-FFh) in Bank 15. The lower half is known
as the “Access RAM” and is composed of GPRs. The
upper half is where the device’s SFRs are mapped.
These two areas are mapped contiguously in the
Access Bank and can be addressed in a linear fashion
by an eight-bit address
The Access Bank is used by core PIC18 instructions
that include the Access RAM bit (the ‘a’ parameter in
the instruction). When ‘a’ is equal to ‘ 1 ’, the instruction
uses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘ 0 ’,
DS39977C-page 114
Note 1:
Bank Select
7
0
ACCESS BANK
0
2:
0
The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>)
to the registers of the Access Bank.
The MOVFF instruction embeds the entire 12-bit address in the instruction.
(2)
0
BSR
USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
(Figure
0
(1)
0
6-6).
1
0
0
FFFh
E00h
000h
100h
200h
300h
F00h
Data Memory
Preliminary
Bank 13
Bank 14
Bank 15
through
Bank 0
Bank 1
Bank 2
Bank 3
however, the instruction is forced to use the Access
Bank address map. In that case, the current value of
the BSR is ignored entirely.
Using this “forced” addressing allows the instruction to
operate on a data address in a single cycle without
updating the BSR first. For 8-bit addresses of 60h and
above, this means that users can evaluate and operate
on SFRs more efficiently. The Access RAM below 60h
is a good place for data values that the user might need
to access rapidly, such as immediate computational
results or common program variables.
Access RAM also allows for faster and more code
efficient context saving and switching of variables.
The mapping of the Access Bank is slightly different
when the extended instruction set is enabled (XINST
Configuration bit = 1 ). This is discussed in more detail
in
Indexed Literal Offset Mode”
6.3.3
PIC18 devices may have banked memory in the GPR
area. This is data RAM which is available for use by all
instructions. GPRs start at the bottom of Bank 0
(address 000h) and grow upwards towards the bottom of
the SFR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other Resets.
Section 6.6.3 “Mapping the Access Bank in
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
GENERAL PURPOSE
REGISTER FILE
7
1
1
1
1
2011 Microchip Technology Inc.
From Opcode
1
1
1
1
.
1
1
1
1
(2)
1
1
1
0
1
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