MCIMX514AJM6C Freescale Semiconductor, MCIMX514AJM6C Datasheet
MCIMX514AJM6C
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MCIMX514AJM6C Summary of contents
Page 1
... Changed ENGcm10259 number to ENGcm10260 • Changed ENGcm10267 number to ENGcm10272 • Removed ENGcm10353 - duplicate of ENGcm10356 • Removed ENGcm10342 - duplicate of ENGcm10344 • Added ENGcm11161 and updated ENGcm11065 workaround. © Freescale Semiconductor, Inc., 2010. All rights reserved. Table 1. Document Revision History Substantive Changes IMX51CE Rev. 3, 11/2010 ...
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... Added Linux and WinCE BSP status information 2 Substantive Changes ENGcm09107 ENGcm09399 ENGcm11189 ENGcm11199 ENGcm11205 ENGcm07782 ENGcm11208 ENGcm08316 ENGcm11226 ENGcm11249 ENGcm11408 for removing HS/FS USB TLL support. ENGcm10716 ENGcm11353 ENGcm11226 ENGcm08971 ENGcm08842 ENGcm11422 ENGcm11403 Chip Errata for the i.MX51, Rev. 3 ENGcm11244 Freescale Semiconductor ...
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... MCIMX51 3.0 MCIMX51 3.0 MCIMX51 3.0 MCIMX51 3.0 MCIMX51 3.0 MCIMX51 3.0 MCIMX51 3.0 MCIMX51 3.0 MCIMX51 3.0 MCIMX51 3.0 MCIMX51 3.0 1 Part numbers with a PC prefix indicate non-production engineering parts. Freescale Semiconductor Package Device Marking PCIMX511AJM6C PCIMX512CJM6C MCIMX512DJM8C PCIMX513CJM6C MCIMX513DJM8C ...
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... No fix scheduled 19 No fix scheduled 21 No fix scheduled 23 No fix scheduled 25 No fix scheduled 26 No fix scheduled 28 No fix scheduled 30 No fix scheduled -Clarified fix scheduled 33 No fix scheduled 35 No fix scheduled 37 No fix scheduled 39 No fix scheduled 41 Freescale Semiconductor ...
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... EPIT: Possibility of additional pulse on src_clk when switching between clock sources ENGcm06969 ESDCTL: Precharge after write may be delayed ENGcm08971 eSDCTL: ESDGPR register bits are not readable ENGcm06545 eSDHC: Buffer overrun prevents CPU polling reads when WML is set as 1 Freescale Semiconductor Name CCM CSPI DAP DPLL eCSPI EMI EPIT ...
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... No fix scheduled 73 No fix scheduled 74 No fix scheduled 75 No fix scheduled 76 Software driver library fix 77 planned for next release No fix scheduled 78 No fix scheduled 79 No fix scheduled 80 No fix scheduled 81 No fix scheduled 82 No fix scheduled 83 No fix scheduled 84 Freescale Semiconductor ...
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... NFC: Unlock registers are reset during warm reset ENGcm09970 NFC: NFC does not work properly when RBB_MODE = 0 (read status) ENGcm09980 NFC: Misses read data when working in Symmetric mode with clock ratio 1:2, and using a 16-bit Flash bus width Freescale Semiconductor Name 2 C does not work IPU M4IF NFC Chip Errata for the i ...
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... No fix scheduled 116 No fix scheduled 117 No fix scheduled 118 No fix scheduled 120 No fix scheduled 121 No fix scheduled 122 No fix scheduled 123 No fix scheduled 124 No fix scheduled 125 No fix scheduled 126 No fix scheduled 127 No fix scheduled 128 No fix scheduled 129 Freescale Semiconductor ...
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... USB: Issue when USB_CLK_ROOT Clock is enabled while PHCD bit is set ENGcm11249 USB: USB-OTG port ULPI interface is not supported ENGcm11408 USB: High Speed Transceiverless Logic interface (HS-TLL) and Full Speed Transceiverless Logic interface (FS-TLL) USB interfaces are not supported Freescale Semiconductor Name RTIC SAHARA SRTC SSI USB VPU Chip Errata for the i ...
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... Cb and Cr 10 Name Chip Errata for the i.MX51, Rev. 3 Solution Page Case fix scheduled 149 Cases 2 and 3 - fixed in last firmware release for silicon rev. 2.0 and rev 3.0 No fix scheduled 151 No fix scheduled 152 Fixed in firmware 153 No fix scheduled 154 Freescale Semiconductor ...
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... Linux BSP Status: No software workaround required. Linux BSP does not use unaligned access to the AIPS registers. WinCE BSP Status: No software workaround required. WinCE BSP does not use unaligned access to the AIPS registers. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm07298 11 ...
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... Proposed Solution: No fix scheduled. 1. Category 2 defined as: Behavior that contravenes the specified behavior and that can limit or severely impair the intended use of specified features, but does not render the product unusable in all or the majority of applications. 12 Chip Errata for the i.MX51, Rev Freescale Semiconductor ...
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... Fixed in Linux BSP release 10.03.00. Shared Device memory type is not used. But PRRR setup codes were added before enabling MMU in the bootloader. WinCE BSP Status: Fixed in WinCE BSP release ER10_SP1. Workaround implemented. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm09830 13 ...
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... The second option is to set bit 16 in the CP15 Auxiliary Control Register. This causes a pipeline flush on every write to the CP15 register and ensures that the RAW hazard condition does not 1. Category 3 defined as: Behavior that is not the originally intended behavior but should not cause any problems in applications. 14 Chip Errata for the i.MX51, Rev Freescale Semiconductor ...
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... CP15 registers. OSBench indicates a performance impact 14% for a subset of the OSBench tests (interprocess PSL calls). An analysis of the OSBench performance on Cortex-A8 determined that interprocess PSL calls generate excessive cache maintenance. Freescale Semiconductor ; read Aux Ctl Register ; set bit write Aux Ctl Register Chip Errata for the i ...
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... MMU. Alternatively, the CSU can be configured to transform User access to Privileged on addresses used by PAGE TABLE. Proposed Solution: No fix scheduled. Linux BSP Status: System memory bus has no user mode protection, so this is not applicable. 16 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
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... WinCE BSP Status: No software workaround is available. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm04786 17 ...
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... No software workaround required. System does not perform cache maintenance in non-secure mode. 1. Category 2 defined as: Behavior that contravenes the specified behavior and that can limit or severely impair the intended use of specified features, but does not render the product unusable in all or the majority of applications. 18 Chip Errata for the i.MX51, Rev Freescale Semiconductor ...
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... Category 2 defined as: Behavior that contravenes the specified behavior and that can limit or severely impair the intended use of specified features, but does not render the product unusable in all or the majority of applications. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm07784 1 ...
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... BSP implements software workaround to replace clean cache line operation with Clean-and-Invalidate cache line operation. There may be a performance penalty due to the undesired invalidation of the cache line when invoking OEMCacheRangeFlush to clean individual cache lines. 20 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
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... Category 2 defined as: Behavior that contravenes the specified behavior and that can limit or severely impair the intended use of specified features, but does not render the product unusable in all or the majority of applications. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm07786 1 ...
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... Does not apply to Linux BSP because page coloring guidelines are followed for VIPT cache types. WinCE BSP Status: It was determined that the conditions required by the erratum do not occur within WinCE, and therefore, no software workaround is required. 22 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
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... L1 and L2 cache and written out to main memory. 1. Category 2 defined as: Behavior that contravenes the specified behavior and that can limit or severely impair the intended use of specified features, but does not render the product unusable in all or the majority of applications. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm07782 1 ...
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... The software workaround is to disable write allocate in the Level 2 cache in the bootloader. This workaround has performance penalty. WinCE BSP Status: Workaround implemented in WinCE BSP release ER1. Write allocate is disabled in L2 cache control register. This workaround impacts performance. 24 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
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... Write allocate is disabled in L2 cache control register. 1. Category 2 defined as: Behavior that contravenes the specified behavior and that can limit or severely impair the intended use of specified features, but does not render the product unusable in all or the majority of applications. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm04758 1 ...
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... Linux BSP Status: Not implemented because the swap instructions are not used. They are deprecated for ARMv7. 1. Category 3 defined as: Behavior that is not the originally intended behavior but should not cause any problems in applications. 26 Chip Errata for the i.MX51, Rev Freescale Semiconductor ...
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... Kernel Interlocked APIs do not make use of swap instructions. No usage of swap instruction found in the public/private code that Freescale has access to. Confirmed that swap instruction is not used in the WinCE OS. Freescale codecs and customer application code must avoid usage of swap instructions. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm04761 27 ...
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... Category 2 defined as: Behavior that contravenes the specified behavior and that can limit or severely impair the intended use of specified features, but does not render the product unusable in all or the majority of applications read register ; L1NEON caching enable ; write register. ; read register ; L2 load data forwarding disable ; write register Chip Errata for the i.MX51, Rev Freescale Semiconductor ...
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... If the use of the NS world is never enabled, then the issue cannot occur. The hazard occurs between the NS and S worlds which does not get flushed properly, and data gets forwarded from the L2 data buffers. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm04759 ...
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... The software workaround is to disable write allocate in the Level 2 cache. This workaround has performance penalty. 1. Category 2 defined as: Behavior that contravenes the specified behavior and that can limit or severely impair the intended use of specified features, but does not render the product unusable in all or the majority of applications. 30 Chip Errata for the i.MX51, Rev Freescale Semiconductor ...
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... WinCE BSP Status: Workaround implemented in WinCE BSP release ER1. Write allocate is disabled in L2 cache control register. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm04760 31 ...
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... WinCE BSP Status: Workaround implemented in WinCE BSP release SDK_1.6. In the register AMC of the ARM Platform (0xBASE_0018), the bit ALPEN must be set to 1 and ALP[2:0] must be set to ‘000’. Other combinations are reserved and must be avoided. 32 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
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... Category 2 defined as: Behavior that contravenes the specified behavior and that can limit or severely impair the intended use of specified features, but does not render the product unusable in all or the majority of applications. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm10700 1 ...
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... No fix scheduled. Linux BSP Status: No software workaround is implemented because performance counters are not used and are only for debug. WinCE BSP Status: WinCE BSP currently does not use the performance counters. No BSP change required. 34 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
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... Not required because Device memory type is not user space accessible. WinCE BSP Status: Workaround implemented in WinCE BSP release APR2010. 1. Category 3 defined as: Behavior that is not the originally intended behavior but should not cause any problems in applications. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm10716 1 ...
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... ENGcm10716 The memory which is Device Shared should be mapped as Normal Outer/Inner Non-Cacheable. This is the preferred memory type for RAM memory mapped as NCB. Customer software must avoid Device memory types. 36 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
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... MRC p15, 0, R1, c1, c0 read Aux Ctl Register ORR R1, R1 #(1 << set IBE to 1 MCR p15, 0, R1, c1, c0 write Aux Ctl Register 1. Category 3 defined as: Behavior that is not the originally intended behavior but should not cause any problems in applications. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm10701 1 ...
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... Proposed Solution: No fix scheduled. Linux BSP Status: No software workaround is implemented because IBE is not set as 1. WinCE BSP Status: WinCE BSP does not set the IBE bit. BTB invalidate operations will be NOPs. No BSP change required. 38 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
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... MMU fault and attempts to re-execute the original instruction. Re-executing the instruction regenerates the Watchpoint debug event, but now the page is properly patched up. Proposed Solution: No fix scheduled. 1. Category 3 defined as: Behavior that is not the originally intended behavior but should not cause any problems in applications. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm10703 1 . ...
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... No software workaround is implemented because the watchpoints are for debug only. WinCE BSP Status: Watchpoints are only used by debug software. WinCE uses Microsoft kernel debugger that does not utilize hardware watchpoints. No BSP change required. 40 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 41
... The WinCE BSP configures the VFP for run-fast mode (default NAN enabled, flush-to-zero enabled subject to the erratum. WinCE BSP does not specifically configure RP rounding 1. Category 3 defined as: Behavior that is not the originally intended behavior but should not cause any problems in applications. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm10724 1 ...
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... Our FP support comes from a DLL provided by ARM. The ARM DLL should avoid the specific rounding mode associated with the erratum. Need to ensure RP rounding mode is not enabled. 42 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
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... The value of changing a memory region from cacheable to non-cacheable 1. Category 2 defined as: Behavior that contravenes the specified behavior and that can limit or severely impair the intended use of specified features, but does not render the product unusable in all or the majority of applications. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm11205 1 ...
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... The workaround code must independently ensure that the correct page table entry is present. Proposed Solution: No fix scheduled. Linux BSP Status: Not required because set/way is used in cache maintenance. WinCE BSP Status: Not implemented. 44 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
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... Device memory type. In this case, need to avoid potential memory consistence issues and perform Data Synchronization Barrier (DSB) before other DMA engine access the region for read, as the Write Buffer is enabled. Proposed Solution: No fix scheduled. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm11422 45 ...
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... The CCSR[2] must be cleared in separate register access prior to changing CCSR[8:7]. Proposed Solution: No fix scheduled. A clarification is added to the reference manual. Linux BSP Status: Partially implemented. Full implementation in next release. WinCE BSP Status: Implemented. 46 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
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... This causes the system to hang. Projected Impact: None. User should refrain from disabling the EMI int1 clock. Workarounds: None. Proposed Solution: No fix scheduled. A clarification is added to the reference manual. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm08842 47 ...
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... CSPI, the software can assume that it is the result of an Overrun condition. Proposed Solution: No fix scheduled. Linux BSP Status: Not required. DMA mode is not enabled in Linux BSP. WinCE BSP Status: Implemented. 48 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
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... ZEffectZ: preventing reliable access of the IPs by DAP without CPU intervention. Workarounds: Ensure the core is in the active mode and the debug IPs are accessed through the core. Proposed Solution: No fix scheduled. Linux BSP Status: No software workaround. WinCE BSP Status: No software workaround. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm04789 49 ...
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... When RVI (the debugger) connects to the i.MX51 (the target), the scan chain can not automatically be built. Workarounds: The scan chain must either be manually built or an external RVI script must be used. Proposed Solution: No fix scheduled. Linux BSP Status: No software workaround. WinCE BSP Status: No software workaround. 50 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
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... A software delay for a fixed amount of time based on TOG_COUNT after the TOG_DIS bit is set. Proposed Solution: No fix scheduled. Linux BSP Status: Not required because not used. WinCE BSP Status: Not required. WinCE BSP does not use the TOG_DIS bit. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm04750 51 ...
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... A hardware solution is to place an inverter on the SS signal and program SSB_POL = 0. Proposed Solution: No fix scheduled. Linux BSP Status: Workaround implemented in Linux BSP release 09.12.00. WinCE BSP Status: Workaround implemented in WinCE BSP release ER10_SP1. 52 NOTE Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
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... BURST_LENGTH parameter. Proposed Solution: No fix scheduled. Linux BSP Status: Not implemented because eCSPI slave mode is not supported in the Linux BSP driver. WinCE BSP Status: Not required. WinCE BSP does not support slave mode. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm10183 53 ...
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... EMI registers. DDR content is preserved even though a cold reset is issued because in Sleep mode the memory is already in self refresh. Workarounds: None. Proposed Solution: No fix scheduled. Linux BSP Status: No software workaround. WinCE BSP Status: No software workaround. 54 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 55
... In case this mechanism is still required, it can be successfully operated with non-burst access. Workarounds: Exclusive access to EMI works only if the tagged address is accessed directly. The access detection mechanism fails if the tagged location is written by consecutive burst access. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm09424 55 ...
Page 56
... The issue can be avoided if the software constrains the regular write to the tagged location to use non-burst access or use and addresses corresponding to the first word in the burst. Proposed Solution: No fix scheduled. Linux BSP Status: Not required because it does not happen. WinCE BSP Status: Not required. 56 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 57
... Projected Impact: WEIM 8-bit memory devices are supported according to above description. Workarounds: None. Proposed Solution: No fix scheduled. A clarification is added in the reference manual. Linux BSP Status: No software workaround. WinCE BSP Status: No software workaround. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm11244 57 ...
Page 58
... Re-enable EPIT EPITCR[ (EN = 1), that is, enable EPIT 8. Reconfigure output and interrupt Proposed Solution: No fix scheduled. Linux BSP Status: Not implemented because EPIT is not used now. WinCE BSP Status: Not required. BSP does not switch EPIT clk src. 58 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
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... Workarounds: None required, as the performace degradation is approximately 0.1%. Proposed Solution: No fix scheduled. Linux BSP Status: No software workaround required. WinCE BSP Status: No software workaround required. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm06969 59 ...
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... The Enhanced SDRAM General Purpose Register (ESDGPR register at address 0xBASE+0x1034) bits 19 through 31 do not return correct value on read. The write operation works according to the specification. Projected Impact: No functional impact. Workarounds: None. Proposed Solution: No fix scheduled. The reference manual is updated accordingly. 60 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
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... A read when WML is set to 2 can still be split into two successive reads. Proposed Solution: No fix scheduled. Linux BSP Status: Not required because WML is not 1. WinCE BSP Status: Not required. This case does not happen in WinCE BSP. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm06545 61 ...
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... The eSDHC can not finish write operations after encountering a block gap stop. Workarounds: Do not use stop-at-block-gap during write operations. Proposed Solution: No fix scheduled. Linux BSP Status: Not required because the stop-at-block-gap feature is not implemented. WinCE BSP Status: Not required. Stop-at-block-gap is not supported in current driver. 62 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 63
... Proposed Solution: No fix scheduled. Linux BSP Status: Does not occur in BSP. WinCE BSP Status: Workaround implemented in WinCE BSP release ER1. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm06706 63 ...
Page 64
... Set the BLKCNT to the maximum value in Block Attributes Register (BLKATTR) (0xFFFF for 65535 blocks) Proposed Solution: No fix scheduled. Linux BSP Status: Infinite Block Transfer Mode is not supported in BSP. WinCE BSP Status: Not required. BSP does not have such case in driver. 64 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 65
... Do not use SDMA with the HS-I Proposed Solution: No fix scheduled. Linux BSP Status: Not required because DMA mode is not enabled for HS-I WinCE BSP Status: Workaround implemented in WinCE BSP release ER7. Freescale Semiconductor NOTE 2 C module and not to the two standard current Linux BSP ...
Page 66
... DINT and TC bit is received when read operation is done, clear HCKEN bit to re-enable the hclk auto-gating feature. See drivers/mmc/host/mx_sdhci.c (SDHCI_CLOCK_HLK_EN). WinCE BSP Status: Already implemented workaround of disabling auto clock gating feature while a command or data is in progress. 66 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 67
... Do not use RD_WML and [{(BLK_SIZE + 3) ÷ 4}% RD_WML = 1) configuration for read operations. Proposed Solution: No fix scheduled. Linux BSP Status: Not required because WML is not 1. WinCE BSP Status: Not required. BSP does not have such case now. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm09149 67 ...
Page 68
... Proposed Solution: No fix scheduled. Linux BSP Status: Not required because Linux driver avoids this issue. WinCE BSP Status: Partially implemented. Full implementation in next release. 68 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 69
... In ADMA2 mode this workaround is not feasible due to ENGcm11161. Proposed Solution: No fix scheduled. Linux BSP Status: Not required because ADMA mode is not enabled. WinCE BSP Status: Not required. BSP does not have such case. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm11065 69 ...
Page 70
... Bytes valid data 2 Bytes valid data + 2 Byte dummy data 4 Bytes valid data 4 Bytes valid data 4 Bytes valid data 4 Bytes valid data 4 Bytes valid data 2 Bytes valid data + 2 Byte dummy data 70 block size ⋅ 4 ----------------------- - 4 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 71
... Alternatively, the PIO mode can be used if the block size is non-4 byte aligned. Proposed Solution: No fix scheduled. Linux BSP Status: Not required because ADMA mode is not enabled. WinCE BSP Status: Not required. BSP does not have such case. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm11104 71 ...
Page 72
... Software workaround is to always program TRANS descriptor as the last descriptor. Proposed Solution: No fix scheduled. Linux BSP Status: Not required because ADMA mode is not enabled. WinCE BSP Status: Not required. BSP does not have such case. 72 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 73
... DAT1 signal, if the DAT1 line is still low. 4. Re-enable CINTEN bit in IRQSTATEN and IRQSIGEN. Proposed Solution: No fix scheduled. Linux BSP Status: Workaround implemented in Linux BSP release 09.12.00. WinCE BSP Status: Not implemented yet. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm09399 73 ...
Page 74
... The problem is identified by receiving the CMD CRC error and CMD Index error. Once this issue occurs, one can send the same CMD again until operation is successful. Proposed Solution: No fix scheduled. 74 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 75
... The FEC cannot use the NFC to access memory. Workarounds: The FEC should use the DDR for its buffer. Proposed Solution: No fix scheduled. Linux BSP Status: The case does not occur in Linux BSP. WinCE BSP Status: Implemented. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm04798 75 ...
Page 76
... SCLK is required). Proposed Solution: No fix scheduled. Linux BSP Status: Not required because GPT parent is not changed in current code. WinCE BSP Status: Workaround implemented in WinCE BSP release ER7. 76 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 77
... Proposed Solution: No hardware fix scheduled. This issue will be addressed in the software drivers in the next driver release. WinCE BSP Status: Workaround implemented in WinCE BSP release ER1004 (for i.MX51). Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm11199 77 ...
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... WinCE BSP Status: Workaround implemented in WinCE BSP Address Issue 2 C starts generating high frequency clocks on the SCL line. This 2 C bus in an actual application reaches that number. NOTE 2 C module and not to the two standard Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 79
... Proposed Solution: No fix scheduled. Linux BSP Status not supported. WinCE BSP Status: Workaround implemented in WinCE BSP. Freescale Semiconductor C: After a read operation, the HS-I NOTE 2 C module and not to the two standard Chip Errata for the i.MX51, Rev. 3 ENGcm08218 2 C does not operate ...
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... AUTO_RSTA should be disabled. Proposed Solution: No fix scheduled. Linux BSP Status not supported. WinCE BSP Status: Workaround implemented in WinCE BSP Auto Restart not working NOTE 2 C module and not to the two standard Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 81
... Proposed Solution: No fix scheduled. Linux BSP Status not supported. WinCE BSP Status: Workaround implemented in WinCE BSP. Freescale Semiconductor C: Clock Stretching Does not Work NOTE 2 C module and not to the two standard Chip Errata for the i.MX51, Rev. 3 ENGcm09179 2 C controller after every byte is sent, the ...
Page 82
... C modules. Proposed Solution: No fix scheduled. Linux BSP Status not supported. WinCE BSP Status: Workaround implemented in WinCE BSP HICR[HIIEN] bit does not mask the interrupts NOTE 2 C module and not to the two standard Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 83
... Proposed Solution: No fix scheduled. Linux BSP Status not supported. WinCE BSP Status: Workaround implemented in WinCE BSP. Freescale Semiconductor C: Read after write from an external device fails NOTE 2 C module and not to the two standard Chip Errata for the i.MX51, Rev. 3 ENGcm09404 83 ...
Page 84
... C is not supported. WinCE BSP Status: Workaround implemented in WinCE BSP TDC_ZERO and RDC_ZERO status bits are not cleared NOTE 2 C module and not to the two standard 2 C interrupt and enable it again after generating the start Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 85
... Proposed Solution: No fix scheduled. Linux BSP Status not supported. WinCE BSP Status: Workaround implemented in WinCE BSP. Freescale Semiconductor C: The associated divider of the HIFSFDR does not operate NOTE 2 C module and not to the two standard Chip Errata for the i.MX51, Rev. 3 ENGcm09396 85 ...
Page 86
... This erratum only applies to the HS modules. Proposed Solution: No fix scheduled. Linux BSP Status not supported High Speed mode of HS module can not be used. NOTE 2 C module and not to the two standard Chip Errata for the i.MX51, Rev does not work Freescale Semiconductor ...
Page 87
... IC as 0xFE. The result is equivalent in observation - the graphics component is fully opaque in the combined image when using the value 0xFE, just with the value 0xFF. The resultant combined pixel may be very slightly different, but this change is negligible and non-discernible. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm09277 87 ...
Page 88
... No fix scheduled. Linux BSP Status: Implemented, but not sure if pixel mode works or is valid for all LCDs. WinCE BSP Status: There is no DVFS transitions which affect the IPU, so this erratum has no effect on the system. 88 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 89
... DP. Proposed Solution: No fix scheduled. Linux BSP Status: This case does exist. The BSP performs CSC for the graphic layer. The workaround is to use software CSC instead of enabling CSC2. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm09634 89 ...
Page 90
... Not implemented. The case may occur using PP and PRP at the same time while using IC local alpha blending function for both tasks. But no plan to fix it because this case is required by the users and the issue impact is small. WinCE BSP Status: WinCE BSP does not have such case. 90 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 91
... No fix scheduled. Linux BSP Status: BSP follows the clarification. WinCE BSP Status: Partially implemented. Need to fully align with this workaround on next BSP release. Freescale Semiconductor Table 4 is required for proper display and sensor interfaces Table 4. Bypass Mode Registers Setup Address Access ...
Page 92
... LPACK register. The LPACK register indicates that the M4IF is idle and the step-by-step can be enabled. The difference between the regular procedure of LPMD and this procedure is that the EMI clocks remain ON. Proposed Solution: No fix scheduled. Linux BSP Status: Not required. WinCE BSP Status: Not required. 92 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 93
... None. Workarounds: Initialization must be performed first, followed by enabling the M4IF power saving. Proposed Solution: No fix scheduled. Linux BSP Status: Workaround implemented in Linux BSP release 09.12.00. WinCE BSP Status: Workaround implemented in WinCE BSP. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm10678 93 ...
Page 94
... M4IF and DDR control programing must meet this restriction: tXSR (DDR parameter) + tRFC (DDR parameter) < 8 × FPST (M4IF parameter) Proposed Solution: No fix scheduled. Linux BSP Status: Workaround implemented in Linux BSP release 09.12.00. WinCE BSP Status: Workaround implemented in WinCE BSP. 94 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 95
... The arbitration domain selected by MDCR/RARB MDSR8 The arbitration domain selected by MDCR/RARB SBS0 The arbitration domain selected by MDCR/RARB SBS1 The arbitration domain selected by MDCR/RARB Freescale Semiconductor Table 5. List of Impacted Registers Required Master/Slave to be Active for Read Action to Succeed Chip Errata for the i.MX51, Rev. 3 ENGcm11226 95 ...
Page 96
... No impact on regular functionality. The status registers are usually accessed for debugging purposes. Workarounds: Enable the relevant M4IF masters or slaves clocks for the status read. Proposed Solution: No fix scheduled. 96 Required Master/Slave to be Active for Read Action to Succeed Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 97
... The software must launch a status-read command at the end of auto_erase, auto_prog or copy_back operations. Proposed Solution: No fix scheduled. Linux BSP Status: Workaround implemented in Linux BSP release 09.12.00. WinCE BSP Status: Workaround implemented in WinCE BSP release ER9. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm09044 97 ...
Page 98
... NAND. This restricts 8-sym ECC operation to 8-bit NAND devices. Workarounds: None. Proposed Solution: No fix scheduled. The reference manual is updated accordingly. Linux BSP Status: No software workaround required. WinCE BSP Status: No plan to support as there is no NAND Flash on EVK. 98 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 99
... Both options affect the overall performance. Proposed Solution: No fix scheduled. Linux BSP Status: Not required because BSP does not use this feature. WinCE BSP Status: No plan to support as there is no NAND Flash on EVK. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm09575 99 ...
Page 100
... As there is no difference between LOCK and LOCK_TIGHT modes, the software should not use LOCK_TIGHT mode. Proposed Solution: No fix scheduled. Linux BSP Status: Not required because BSP does not use this feature. WinCE BSP Status: No plan to support as there is no NAND Flash on EVK. 100 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 101
... It should be handled in the software done now for the Windows and Linux drivers. Proposed Solution: No fix scheduled. Linux BSP Status: Not required because BSP does not use this feature. WinCE BSP Status: No plan to support as there is no NAND Flash on EVK. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm06982 101 ...
Page 102
... Proposed Solution: No fix scheduled. Linux BSP Status: Not required because BSP does not use this feature. WinCE BSP Status: No plan to support as there is no NAND Flash on EVK. 102 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 103
... Do not to apply software reset for the above conditions. Proposed Solution: No fix scheduled. Linux BSP Status: Not required because BSP does not use this feature. WinCE BSP Status: Not required. BSP does not have such case. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm09186 103 ...
Page 104
... If RBB_MODE = used, then after the Automatic program, Automatic CopyBack0 and Automatic CopyBack1 operations, Status read should be done explicitly. Proposed Solution: No fix scheduled. Linux BSP Status: Workaround implemented in Linux BSP release 09.12.00. WinCE BSP Status: Workaround implemented in WinCE BSP release ER9. 104 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 105
... Unlocking the registers cause a minor delay until the NFC is ready to work. Proposed Solution: No fix scheduled. Linux BSP Status: Workaround implemented in Linux BSP release 09.12.00. WinCE BSP Status: Not required. Eboot sets the registers properly. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm09394 105 ...
Page 106
... Connect the ready/busy signal from the Flash to the i.MX51 and program RBB_MODE = 1. However, using this workaround restricts the number of CS supported to 4 instead of 8. Proposed Solution: No fix scheduled. Linux BSP Status: Not required because using rbb_mode = 1. WinCE BSP Status: Software workaround implemented. 106 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 107
... Proposed Solution: No fix scheduled. Linux BSP Status: Not required because BSP does not have such case. WinCE BSP Status: Not required because the 16-bit NAND is not supported with current WinCE BSP. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm09980 107 ...
Page 108
... Do not use the combination of parameters/conditions described above. Proposed Solution: No fix scheduled. Linux BSP Status: Not required because BSP does not use this feature. WinCE BSP Status: Not required because BSP does not use this feature. 108 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 109
... Do not use the combination of parameters/modes described above. Proposed Solution: No fix scheduled. Linux BSP Status: Not required because such devices are not available yet. WinCE BSP Status: Not required because such devices are not available yet. Freescale Semiconductor NOTE Chip Errata for the i.MX51, Rev. 3 ENGcm10036 109 ...
Page 110
... Avoid using the NFC_RST bit of the NFC_CONFIGURATION1 register. Proposed Solution: No fix scheduled. Linux BSP Status: Workaround implemented in Linux BSP release 09.12.00. WinCE BSP Status: Not required. BSP does not use this feature. 110 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 111
... Proposed Solution: No fix scheduled. Linux BSP Status: Not required because BSP does not have such case. WinCE BSP Status: Not required because we do not support 16-bit NAND with current WinCE BSP. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm10150 111 ...
Page 112
... Workarounds: Avoid using this combination of conditions. Proposed Solution: No fix scheduled. Linux BSP Status: Not required. BSP does not use this feature. WinCE BSP Status: Not required. BSP does not use this feature. 112 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 113
... NFC can issue one page per connected device. Proposed Solution: No fix scheduled. Linux BSP Status: Not required. BSP does not use this feature. WinCE BSP Status: Not required. BSP does not use this feature. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm10176 113 ...
Page 114
... Do not use these bytes. The Freescale WinCE and Linux BSPs (board support packages) do not use these bytes. Proposed Solution: No fix scheduled. Linux BSP Status: Not required. BSP does not use this feature. WinCE BSP Status: Not required. BSP does not use this feature. 114 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 115
... Connect on board to rb_b0 port a wired-OR of all the ready/busy signals of all the devices. Proposed Solution: No fix scheduled. Linux BSP Status: No software workaround is required. WinCE BSP Status: Not required. BSP does not use this feature. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm10245 115 ...
Page 116
... No fix scheduled. Linux BSP Status: No complete software workaround. WinCE BSP Status: Software workaround implemented. It can alleviate the issue, but cannot completely solve it. Such use case (4-bit ECC) is rare under current market environment. 116 1 --------------- - ⋅ Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 117
... ARM must not request more the 2 data words at a time. Proposed Solution: No fix scheduled. Linux BSP Status: Not required. BSP does not use this feature. WinCE BSP Status: Not required. BSP does not use this feature. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm10344 117 ...
Page 118
... NFC internal RAM between the AXI host address and the NAND address) must be set to 0.5 Kbyte (set FMP = 4). In read operation, the FMP can be set to any value that is less than or equal to 0.5 Kbyte, (that is, setting FMP to either 4). 118 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 119
... Proposed Solution: No fix scheduled. Linux BSP Status: Not required. BSP does not use this feature. WinCE BSP Status: Not required. BSP does not use this feature. Freescale Semiconductor ENGcm10967. Chip Errata for the i.MX51, Rev. 3 ENGcm10676 119 ...
Page 120
... ADDR_ADD0 to repeat the operation for the next device. Proposed Solution: No fix scheduled. Linux BSP Status: Not required. BSP does not use this feature. WinCE BSP Status: Not required. BSP does not use this feature. 120 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 121
... Avoid using interleaved mode in TOO configuration. Proposed Solution: No fix scheduled. Linux BSP Status: Not required. BSP does not use this feature. WinCE BSP Status: Not required. BSP does not use this feature. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm11043 121 ...
Page 122
... Workarounds: Perform atomic status read operation (that is, send command 70 followed by single toggle of RE). Proposed Solution: No fix scheduled. Linux BSP Status: Workaround implemented in Linux BSP release 09.12.00. WinCE BSP Status: Software workaround implemented. 122 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 123
... This results in small performance degradation as the supported ONFI1.0 wb NAND can run MHz. Proposed Solution: No fix scheduled. Linux BSP Status: Workaround implemented in Linux BSP release 09.12.00. Freescale Semiconductor / the period from WE write enable signal HIGH to R MCIMX51) for detailed modes description. Chip Errata for the i.MX51, Rev. 3 ...
Page 124
... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...
Page 125
... Take measures to avoid such cases. Leaving the unused interface supply open, does not cause any issue. The issue occurs only when a supply is grounded through a small resistor. The best design practice is to apply power to all the supply rails. Proposed Solution: No fix scheduled. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm10640 125 ...
Page 126
... Having this situation for short periods (such as during power up sequence) should not cause any damage. Alternatively, if high impedance with a low resistive path to ground is projected on the supply, then leakage is negligible. Proposed Solution: No fix scheduled. 126 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 127
... DCD. Projected Impact: Can not execute serial boot if HAB_TYPE is set to Production. Workarounds: Boot loader change or boot to internal memory. Proposed Solution: No fix scheduled. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm10656 127 ...
Page 128
... IOMUX modes as input, with zero level at boot. Workarounds: The only workaround is to avoid setting the unused R/Bx signals to zero during boot, in case of NAND Flash boot mode. Proposed Solution: No fix scheduled. 128 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 129
... Kbyte OneNAND devices boot works properly. Workarounds: For 4 Kbyte devices possible to use only the top half of pages. In this case, ROM reads the boot image properly, but the bottom half of pages are wasted. Proposed Solution: No fix scheduled. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm11353 129 ...
Page 130
... Be aware of limitation. Do not reset RTIC during one time hash mode. Proposed Solution: No fix scheduled. Linux BSP Status: Not required. BSP does not use this feature. WinCE BSP Status: Not required. BSP does not use this feature. 130 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 131
... None. Avoid using the memory region unlock feature in the TrustZone code. Proposed Solution: No fix scheduled. Linux BSP Status: Not required. BSP does not use this feature. WinCE BSP Status: Not required. BSP does not use this feature. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm10974 131 ...
Page 132
... Proposed Solution: No fix scheduled. Linux BSP Status: Not required. Be aware of the limitation. Avoid using a ratio of 1:1 between the AHB and IP buses clock frequencies. WinCE BSP Status: SAHARA is not used in the current BSP release. 132 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 133
... One approach is to authenticate all provisioning software using HAB (high assurance boot) and to lock the LP time and monotonic counters against further changes before allowing unauthenticated software to execute. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm10272 (ENGcm10267) 133 ...
Page 134
... ENGcm10272 (ENGcm10267) Proposed Solution: No fix scheduled. Linux BSP Status: Not required. The driver should ensure it is moving to valid state. 134 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 135
... Enable Tx and Rx in same frame when in Network and Synchronous mode of operation Proposed Solution: No fix scheduled. Linux BSP Status: Workaround implemented in Linux BSP release 09.12.00. WinCE BSP Status: Not required. Network Synchronous mode is not used. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm06571 135 ...
Page 136
... Enable RIE and RFS_EN in SIER 3. Wait for occurrence of RFS 4. Enable/disable TE(SCR[1]) Proposed Solution: No fix scheduled. Linux BSP Status: Not implemented. No failure was observed in Linux BSP. WinCE BSP Status: Workaround implemented in WinCE BSP release ER10_SP1. 136 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 137
... Enable TIE and TFS_EN in SIER. 2. Wait for occurrence of TFS. 3. Disable TE(SCR[1]). Proposed Solution: No fix scheduled. Linux BSP Status: Not required. Asynchronous mode is not used. WinCE BSP Status: Workaround implemented in WinCE BSP release ER10_SP1. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm09222 137 ...
Page 138
... Do not use early FS in Internal FS mode. Proposed Solution: No fix scheduled. Linux BSP Status: Not implemented. No failure was observed in Linux BSP. WinCE BSP Status: Not required. BSP uses word length frame sync. 138 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 139
... Do not use TFR_CLK_DIS feature. Proposed Solution: No fix scheduled. Linux BSP Status: Not required now. BSP does not use I WinCE BSP Status: No workaround is required because WinCE BSP only uses slave mode. Freescale Semiconductor 2 S master mode. Chip Errata for the i.MX51, Rev. 3 ENGcm09212 139 ...
Page 140
... In this case, the probability of actual overflow is higher, but there is a reliable indication that the overflow has actually occurred. Proposed Solution: No fix scheduled. Linux BSP Status: Not required. WinCE BSP Status: Workaround implemented in WinCE BSP. 140 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 141
... The data should be shifted to the right location by the SDMA script or by the software in case of direct access to the register. Proposed Solution: No fix scheduled. Linux BSP Status: Not required because the AC97 mode is not supported. WinCE BSP Status: Not required because the AC97 mode is not supported. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm11138 141 ...
Page 142
... When MX51's USB is operating in device mode, the host should not send two ISO_OUT sequences within less that 200 ns, otherwise i.MX51's USB does not operate correctly. Proposed Solution: No fix scheduled. Linux BSP Status: Not required. WinCE BSP Status: Not implemented. 142 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 143
... Critical for timing-dependent device ISO IN Mult = 3. Workarounds: The SW has to set the MULT < avoid this bug. Proposed Solution: No fix scheduled. Linux BSP Status: Not required. No ISO feature is supported. WinCE BSP Status: Not implemented. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm09110 143 ...
Page 144
... This should not happen in real system because when configured correctly, the USB should not get an error response happens, then Garbage In Garbage Out. Proposed Solution: No fix scheduled. Linux BSP Status: Not required. WinCE BSP Status: Not implemented. 144 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 145
... One can optionally check, during wake-up processing, if the USB clock did run during low-power suspend and only turn on USB_CLK_ROOT when needed. Proposed Solution: No fix scheduled. Linux BSP Status: Not implemented. Plan to fix in next release. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm10636 145 ...
Page 146
... ENGcm10636 WinCE BSP Status: No workaround is required because WinCE BSP does not manage USB_CLK_ROOT this way. 146 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 147
... The erratum does not relate to the functionality of ULPI mode on other USB-Host ports or to the USB-OTG internal PHY interface. Workarounds: Utilize the USB-OTG PHY interface instead or use other USB-Host ports for ULPI interface. Proposed Solution: No fix scheduled. Specification documentation updated accordingly. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm11249 147 ...
Page 148
... HS-TLL and FS-TLL are not supported. These features will be removed from the specification. Projected Impact: Removed support for the option of on board USB connection without transceiver. Workarounds: None. Need to add transceiver for on board connection. Proposed Solution: No fix scheduled. Feature is removed from the reference manual. 148 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 149
... This bug only affects VC-1 stream which have both field interlace mode and frame mode. That kind of bitstream rarely appears in real application case. • Case 2 There is no impact on the normal decoding stream of VPU except the VC-1 Intensity field mode stream. • Case 3 Visual quality impact. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm09125 149 ...
Page 150
... Cases 2 and 3 — Fixed in last firmware release. For case3, the issue is not completely fixed; however, the visual quality is improved. Linux BSP Status: Implemented for case 2 and case 3 in VPU firmware in Linux release 09.12.00. WinCE BSP Status: Implemented for case 2 and case 3 in VPU firmware. 150 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 151
... There is no impact on the encoder, the effect is on H.263-P3 decoder only. Annex I is not implemented/supported by the H.263-P3 encoder. Workarounds: None. No firmware workaround fix feasible. Proposed Solution: No fix scheduled. Linux BSP Status: No workaround. WinCE BSP Status: No workaround. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm10253 151 ...
Page 152
... Workarounds: None. There is no way for firmware workaround fix because the tables and escape run manipulation are done in hardware logic. Proposed Solution: No fix scheduled. Linux BSP Status: No workaround. WinCE BSP Status: No workaround. 152 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 153
... The usage of MPEG1 is rare in new products, so the overall impact is small. Workarounds: There is a firmware workaround. Proposed Solution: No fix scheduled. Linux BSP Status: Fixed in firmware workaround. WinCE BSP Status: Fixed in firmware workaround. Freescale Semiconductor Chip Errata for the i.MX51, Rev. 3 ENGcm10388 153 ...
Page 154
... Huffman tables for Cb and Cr is low result, the overall impact for JPEG decoding should not be significant. Workarounds: None. There is no firmware workaround fix for this erratum. Proposed Solution: No fix scheduled. WinCE BSP Status: Not implemented. 154 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...
Page 155
... Freescale Semiconductor THIS PAGE INTENTIONALLY LEFT BLANK Chip Errata for the i.MX51, Rev. 3 ENGcm10390 155 ...
Page 156
... ENGcm10390 156 Chip Errata for the i.MX51, Rev. 3 Freescale Semiconductor ...