25LC080-I/SN Microchip Technology, 25LC080-I/SN Datasheet - Page 11

IC EEPROM 8KBIT 2MHZ 8SOIC

25LC080-I/SN

Manufacturer Part Number
25LC080-I/SN
Description
IC EEPROM 8KBIT 2MHZ 8SOIC
Manufacturer
Microchip Technology
Datasheets

Specifications of 25LC080-I/SN

Memory Size
8K (1K x 8)
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Speed
2MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (0.154", 3.90mm Width)
Memory Configuration
1K X 8 / 512 X 16
Ic Interface Type
SPI
Clock Frequency
2MHz
Supply Voltage Range
2.5V To 5.5V
Memory Case Style
SOIC
No. Of Pins
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
25LC080-I/SN
Manufacturer:
MCP
Quantity:
1 698
Part Number:
25LC080-I/SN
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
3.6
The Write Status Register (WRSR) instruction allows the
user to select one of four levels of protection for the
array by writing to the appropriate bits in the Status reg-
ister. The array is divided up into four segments. The
user has the ability to write-protect none, one, two, or
all four of the segments of the array. The partitioning is
controlled as shown in Table 3-2.
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bit for the WP pin. The
Write-Protect (WP) pin and the Write-Protect Enable
(WPEN) bit in the Status register control the program-
mable hardware write-protect feature. Hardware write
protection is enabled when WP pin is low and the
WPEN bit is high. Hardware write protection is disabled
when either the WP pin is high or the WPEN bit is low.
When the chip is hardware write-protected, only writes
to nonvolatile bits in the Status register are disabled.
See Table 3-3 for a matrix of functionality on the WPEN
bit.
See Figure 3-5 for the WRSR timing sequence.
FIGURE 3-7:
 2004 Microchip Technology Inc.
SCK
CS
SO
SI
Write Status Register (WRSR)
0
0
0
WRITE STATUS REGISTER TIMING SEQUENCE
1
0
2
instruction
0
3
0
4
0
5
25AA080/25LC080/25C080
High-impedance
0
6
1
7
TABLE 3-2:
7
8
BP1
0
0
1
1
6
9
data to Status register
10
5
11
4
ARRAY PROTECTION
BP0
0
1
0
1
12
3
13
2
Array Addresses
Write-Protected
(0300h - 03FFh)
(0200h - 03FFh)
(0000h - 03FFh)
upper 1/4
14
upper 1/2
1
DS21230D-page 11
none
all
15
0

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