RT8452GS Richtek USA Inc, RT8452GS Datasheet - Page 14

• Manufacturer Part Number: RT8452GS
• Description: IC PWM CTRLR LED DVR 16SOP
• Manufacturer: Richtek USA Inc

Specifications of RT8452GS

• Internal Driver: No
• Type - Primary: Backlight, General Purpose
• Mounting Type: Surface Mount
• Topology: PWM, Step-Down (Buck), Step-Up (Boost)
• Number Of Outputs: 1
• Frequency: 280kHz ~ 420kHz
• Voltage - Supply: 4.5 V ~ 36 V
• Package / Case: 16-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Operating Temperature: -

RT8452
The maximum power dissipation can be calculated by
following formula :
P
Where T
temperature, T
the junction to ambient thermal resistance.
For recommended operating conditions specification of
RT8452, The maximum junction temperature is 125°C.
The junction to ambient thermal resistance θ
dependent. For WQFN-16L 3x3 packages, the thermal
resistance θ
four layers thermal test board. For SOP-16 packages,
the thermal resistance θ
JEDEC 51-7 four layers thermal test board. The maximum
power dissipation at T
following formula :
P
WQFN-16L 3x3 packages
P
SOP-16 packages
The maximum power dissipation depends on operating
ambient temperature for fixed T
resistance θ
derating curves allows the designer to see the effect of
rising ambient temperature on the maximum power
allowed.
www.richtek.com
14
D(MAX)
D(MAX)
D(MAX)
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
Figure 7. Derating Curves for RT8452 Packages
= ( T
= (125°C − 25°C) / (68°C/W) =1.471W for
= (125°C − 25°C) / (95°C/W) =1.053W for
0
J(MAX)
J(MAX)
JA
JA
. For RT8452 packages, the Figure 6 of
A
is 68°C/W on the standard JEDEC 51-7
is the ambient temperature and the θ
is the maximum operation junction
25
− T
Ambient Temperature (°C)
A
) / θ
SOP-16
A
JA
= 25°C can be calculated by
50
JA
is 95°C/W on the standard
WQFN-16L 3x3
75
J(MAX)
Four-Layer PCB
and thermal
100
JA
is layout
125
JA
is
Layout Consideration
PCB layout is very important to design power switching
converter circuits. Some recommended layout guide lines
are suggested as follows :
Place these components as close as possible
The power components L1, D1, C
be placed as close to each other as possible to reduce
the ac current loop area. The PCB trace between power
components must be as short and wide as possible
due to large current flow through these traces during
operation.
The input capacitors C
VCC pin as possible.
Place the compensation components to VC pin as close
as possible to avoid noise pick up.
Connect GND pin ane Exposed Pad to a large ground
plane for maximum power dissipation and noise
reduction.
R
SENS
C
GND
OUT
D1
R
SW
M1
Locate the compensation components to
VC pin as close as possible
PWMOUT
PWMDIM
Figure 8. PCB Layout Guide
L1
GBIAS
R
GATE
C
VC
ISW
VC
ISP
ISN
VC
2
3
4
5
6
7
8
VCC
C
DS8452-01
IN
must be placed as close to
16
15
14
13
12
11
10
9
IN
, M1 and C
GND
VCC
OVP
EN
NC
SS
DCTL
ACTL
September 2010
GND
V
IN
C
C
VCC
SS
OUT
Locate input
capacitor as
close VCC as
possible
must