PACVGA201QR ON Semiconductor, PACVGA201QR Datasheet

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PACVGA201QR

Manufacturer Part Number
PACVGA201QR
Description
VGA PORT COMPANION 16QSOP
Manufacturer
ON Semiconductor
Datasheet

Specifications of PACVGA201QR

Applications
ESD Protection, VGA Port
Current - Supply
10µA
Voltage - Supply
5V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
16-QSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PACVGA201QR
Manufacturer:
CMD
Quantity:
20 000
Features
Applications
©2010 SCILLC. All rights reserved.
May 2010 Rev. 3
Seven channels of ESD protection for all VGA
port connector pins
Meets IEC-61000-4-2 Level-4 ESD requirements
(±8kV contact discharge)
Very low loading capacitance from ESD
protection diodes on VIDEO lines, 4pF typical
TTL to CMOS level-translating buffers with power
down mode for HSYNC and VSYNC lines
Three power supplies for design flexibility
Compact 16-pin QSOP package
RoHS compliant (lead-free) finishing
ESD protection and termination resistors for VGA
(video) port interfaces
Desktop PCs
Notebook computers
LCD monitors
VGA Port Companion Circuit
Product Description
The PACVGA201 provides seven channels of ESD
protection for all signal lines commonly found in a
VGA port. ESD protection is implemented with
current-steering diodes designed to safely handle the
high surge currents encountered with IEC-61000-4-2
Level-4 ESD Protection (±8kV contact discharge).
When a channel is subjected to an electrostatic
discharge, the ESD current pulse is diverted via the
protection diodes into the positive supply rail or
ground where it may be safely dissipated.
Separate positive supply rails are provided for the
VIDEO, DDC_OUT and SYNC channels to facilitate
interfacing with low-voltage video controller ICs and
to provide design flexibility in multiple-supply-voltage
environments.
An internal diode (D
such that V
require
applications where V
D
pins back to the powered down V
ESD protection diodes.
Two non-inverting drivers provide buffering for the
HSYNC and VSYNC signals from the Video
Controller IC (SYNC_IN1, SYNC_IN2). These buffers
accept TTL input levels and convert them to CMOS
output levels that swing between Ground and V
When the PWR_UP input is driven LOW, the SYNC
outputs are driven LOW and the SYNC inputs can
float: no current will be drawn from the VCC3 supply.
The PACVGA201 is housed in a 16-pin QSOP
package with RoHS compliant lead-free finishing.
1
blocks any DC current path from the DDC_OUT
an
CC2
external
is derived from V
1
, in schematic below) is provided
CC3
may be powered down, diode
power
PACVGA201
Publication Order Number:
CC3
supply
CC3
rail via the upper
(V
CC2
PACVGA201/D
input).
does not
CC3
.
In

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PACVGA201QR Summary of contents

Page 1

Features • Seven channels of ESD protection for all VGA port connector pins • Meets IEC-61000-4-2 Level-4 ESD requirements (±8kV contact discharge) • Very low loading capacitance from ESD protection diodes on VIDEO lines, 4pF typical • TTL to CMOS ...

Page 2

Simplified Electrical Schematic V CC1 2 3 VIDEO_1 4 VIDEO_2 5 VIDEO_3 6 GND 9 DDC_OUT1 10 DDC_OUT2 11 SYNC_IN1 13 SYNC_IN2 VIDEO_1 VIDEO_2 VIDEO_3 PWR_UP V CC2 GND View 1 16 ...

Page 3

... PART NUMBERING INFORMATION Package Ordering Part Number QSOP PACVGA201QR PIN DESCRIPTIONS supply pin. This is an isolated supply input for the two sync buffers and SD1 and SD2 supply pin. This is an isolated supply pin for the VIDEO_1, VIDEO_2 and VIDEO_3 ESD supply pin ...

Page 4

Specifications PARAMETER V ,V and V Supply Voltage Inputs CC1 CC2 CC3 Diode Forward Current (one diode conducting at a time) DC Voltage at Inputs VIDEO_1, VIDEO_2, VIDEO_3 DDC_OUT1, DDC_OUT2 SYNC_IN1, SYNC_IN2 Operating Temperature Range Storage Temperature Range Package Power ...

Page 5

PACVGA201 ELECTRICAL OPERATING CHARACTERISTICS SYMBOL PARAMETER I V Supply Current CC1 CC1 I V Supply Current CC3 CC3 V V Pin Open Circuit CC2 CC2 Voltage V Logic High Input Voltage IH V Logic Low Input Voltage IL V Logic ...

Page 6

Application Information A resistor may be necessary between the V required while the PACVGA201 is in the power-down state. The value of this resistor should be chosen such that the extra charge deposited into the V next ESD pulse occurs. ...

Page 7

PACVGA201 Mechanical Details QSOP Mechanical Specifications PACVGA201 devices are supplied in 16-pin QSOP packages. Dimensions are presented below. For complete information on the QSOP-16, see the California Micro Devices QSOP Package Information document. PACKAGE DIMENSIONS QSOP (JEDEC name is SSOP) ...

Page 8

... Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi ...

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