IR3473MTR1PBF International Rectifier, IR3473MTR1PBF Datasheet
IR3473MTR1PBF
Specifications of IR3473MTR1PBF
Related parts for IR3473MTR1PBF
IR3473MTR1PBF Summary of contents
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FEATURES Input Voltage Range: 3V to 27V Output Voltage Range: 0.5V to 12V Continuous 6A Load Capability Constant On‐Time Control Compensation Loop not Required Excellent Efficiency at Very Low Output Currents Programmable Switching Frequency and Soft Start Thermally Compensated Over Current Protection Power Good Output Precision Voltage Reference (0.5V, +/‐1%) Enable Input with Voltage Monitoring Capability Pre‐bias Start Up Thermal Shut Down Under/Over Voltage Fault Protection Forced Continuous Conduction Mode Option Very Small, Low Profile 4mm x 5mm QFN Package BASIC APPLICATION Figure 1: IR3473 Basic Application Circuit 1 February 16, 2011 | ADVANCED DATASHEET | V1.9 | PD97601 ...
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... February 16, 2011 | ADVANCED DATASHEET | V1.9 | PD97601 6A Highly Integrated SupIRBuck Package M M 3473M ?YWW? xxxxx Lot Code Pin 1 Identifier IR3473 TM Tape & Reel Qty Part Number 750 IR3473MTR1PBF 4000 IR3473MTRPBF ...
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FUNCTIONAL BLOCK DIAGRAM 3 February 16, 2011 | ADVANCED DATASHEET | V1.9 | PD97601 6A Highly Integrated SupIRBuck Figure 3: IR3473 Functional Block Diagram IR3473 TM ...
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TYPICAL APPLICATION +3.3V VCC R1 10K R2 10K EN TP4 EN FCCM SW1 EN / FCCM R4 15.8K VSW ISET +3. FCCM 10K 2 ISET PGOOD 3 TP11 PGOOD PGOOD 4 GND1 TP13 SS ...
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PIN DESCRIPTIONS PIN # PIN NAME I/O LEVEL 1 FCCM 2 ISET 3 PGOOD 4, 17 GND Reference 5 FB 6 SS 7 NC 8 3VCBP 9 NC 10 VCC 11 PGND Reference 12 PHASE 13 VIN 14 BOOT VIN + VCC 15 FF ...
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ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. VIN, FF VCC, PGOOD, EN BOOT PHASE BOOT to PHASE ISET PGND to GND All other pins Storage Temperature Range Junction Temperature Range ESD Classification Moisture Sensitivity Level 6 February 16, 2011 | ADVANCED DATASHEET | V1.9 | PD97601 6A Highly Integrated SupIRBuck ‐0.3V to 30V ‐0.3V to 8V ‐0.3V to 38V ‐0.3V to 30V (DC), ‐5V (100ns) ‐0.3V to 8V ‐0.3V to 30V, 30mA ‐0.3V to +0.3V ‐0.3V to 3.9V ‐65°C to 150°C ‐40°C to 150°C JEDEC Class 1C JEDEC Level 3@260°C IR3473 TM ...
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ELECTRICAL SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN Recommended VIN Range Recommended VCC Range Recommended Output Voltage Range Recommended Output Current Range Recommended Switching Frequency Recommended Operating Junction Temperature * PHASE pin must not exceed 30V. ELECTRICAL CHARACTERISTICS Unless otherwise specified, these specifications apply over VIN = 12V, 4.5V < VCC < 5.5V, 0°C ≤ T PARAMETER Control Loop Reference Accuracy On‐Time Accuracy Min. Off Time Soft‐Start Current DCM Comparator Offset Feedback Input Current Supply Current VCC Supply Current (standby) VCC Supply Current (dynamic) FF Shutdown Current Forced Continuous Conduction Mode (FCCM) FCCM Start Threshold FCCM Stop Threshold Gate Drive Deadtime Bootstrap PFET Forward Voltage Upper MOSFET Static Drain‐to‐Source On‐Resistance Lower MOSFET Static Drain‐to‐Source On‐Resistance 7 February 16, 2011 | ADVANCED DATASHEET | V1.9 | PD97601 6A Highly Integrated SupIRBuck SYMBOL ...
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PARAMETER Fault Protection ISET Pin Output Current ISET Pin Output Current Temperature Coefficient Under Voltage Threshold Under Voltage Hysteresis Over Voltage Threshold Over Voltage Hysteresis VCC Turn‐on Threshold VCC Turn‐off Threshold VCC Threshold Hysteresis EN Rising Threshold EN Hysteresis EN Input Current PGOOD Pull Down Resistance PGOOD Delay Threshold Thermal Shutdown Threshold Thermal Shutdown Threshold Hysteresis Note: 1. Guaranteed by design but not tested in production 8 February 16, 2011 | ADVANCED DATASHEET | V1.9 | PD97601 6A Highly Integrated SupIRBuck SYMBOL CONDITIONS On the basis of 25°C On the basis of 25°C, Note 1 Falling V & Monitor FB PGOOD Rising V ...
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TYPICAL OPERATING DATA Tested with demoboard shown in Figure 4, VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, T unless otherwise specified. 90% 85% 80% 75% VIN = 19V 70% VIN = 12V 65% VIN = 8V 60% 55% 50% 45% 0.01 0.1 Load Current (A) Figure 5: Efficiency vs. Load Current for VOUT = 1.05V 350 300 250 200 150 100 ...
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TYPICAL OPERATING DATA Tested with demoboard shown in Figure 4, VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, T otherwise specified. EN PGOOD SS VOUT 5V/div 5V/div 1V/div 500mV/div Figure 11: Startup VOUT PHASE iL 20mV/div 10V/div 500mA/div Figure 13: DCM (I = 0.1A) OUT PGOOD SS VOUT iL 5V/div 1V/div 500mV/div 10A/div Figure 15: Over Current Protection (tested by shorting VOUT to PGND) 10 February 16, 2011 | ADVANCED DATASHEET | V1.9 | PD97601 6A Highly Integrated SupIRBuck 5ms/div 5V/div ...
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TYPICAL OPERATING DATA Tested with demoboard shown in Figure 4, VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, T otherwise specified. VOUT PHASE iL 50mV/div 10V/div 2A/div Figure 17: Load Transient 0‐3A FCCM PHASE VOUT iL 5V/div 10V/div 500mV/div 5A/div Figure 19: DCM/FCCM Transition Figure 21: Thermal Image at VIN = 12V, (IR3473: 64 C, Inductor: 48 C, PCB: 37 11 February 16, 2011 | ADVANCED DATASHEET | V1.9 | PD97601 6A Highly Integrated SupIRBuck 100µs/div 50mV/div 10V/div 5A/div 10µs/div 2V/div 10V/div 500mV/div 5A/div ...
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THEORY OF OPERATION PWM COMPARATOR The PWM comparator initiates a SET signal (PWM pulse) when the FB pin falls below the reference (VREF) or the soft start (SS) voltage. ON‐TIME GENERATOR The PWM on‐time duration is programmed with an external resistor (R ) from the input supply (VIN) to the FF FF pin. The simplified equation for R is shown in equation 1. FF The FF pin is held to an internal reference after EN goes HIGH. A copy of the current in R charges a timing FF capacitor, which sets the on‐time duration, as shown in equation 2. V OUT V ...
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UNDER/OVER VOLTAGE MONITOR The IR3473 monitors the voltage at the FB node through a 350ns filter. If the FB voltage is below the under voltage threshold, UV# is set to LOW holding PGOOD to be LOW. If the FB voltage is above the over voltage threshold, OV# is set to LOW, the shutdown signal (SD) is set to HIGH, MOSFET gates are turned off, and PGOOD signal is pulled low. Toggling VCC or EN will allow the next start up. Figure 24 and 25 show PGOOD status change when UV/OV is detected. The over voltage and under voltage thresholds can be found in the Electrical Specification section. Figure 24: Under/Over Voltage Monitor Figure 25: Over Voltage Protection 13 February 16, 2011 | ADVANCED DATASHEET | V1.9 | PD97601 6A Highly Integrated SupIRBuck OVER CURRENT MONITOR The over current circuitry monitors the output current during each switching cycle. The voltage across the lower MOSFET, VPHASE, is monitored for over current and zero crossing. The minimum lower gate interval allows time to sample VPHASE. The over current trip point is programmed with a resistor from the ISET pin to PHASE pin, as shown in equation 4. ...
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GATE DRIVE LOGIC The gate drive logic features adaptive dead time, diode emulation, and a minimum lower gate interval. An adaptive dead time prevents the simultaneous conduction of the upper and lower MOSFETs. The lower gate voltage must be below approximately 1V after PWM goes HIGH before the upper MOSFET can be gated on. Also, the differential voltage between the upper gate and PHASE must be below approximately 1V after PWM goes LOW before the lower MOSFET can be gated on. The upper MOSFET is gated on after the adaptive delay for PWM = HIGH and the lower MOSFET is gated on after the adaptive delay for PWM = LOW. When FCCM = LOW, the lower MOSFET is driven ‘off’ when the ZCROSS signal indicates that the inductor current is about to reverse direction. The ZCROSS comparator monitors the PHASE voltage to determine when to turn off the lower MOSFET. The lower MOSFET stays ‘off’ until the next PWM falling edge. When the lower peak of the inductor current is above zero, IR3473 operates in continuous conduction mode. The continuous conduction mode can also be selected for all load current levels by pulling FCCM to HIGH. Whenever the upper MOSFET is turned ‘off’, it stays ‘off’ for the Min Off Time denoted in the Electrical Specifications. This minimum duration allows time to recharge the bootstrap capacitor and allows the over current monitor to sample the PHASE voltage. COMPONENT SELECTION Selection of components for the converter is an iterative process which involves meeting the specifications and tradeoffs between performance and cost. The following sections will guide one through the process. Inductor Selection Inductor selection involves meeting the steady state output ripple requirement, minimizing the switching loss of the upper MOSFET, meeting transient response specifications and minimizing the output capacitance. ...
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Output Capacitor Selection Selection of the output capacitor requires meeting voltage overshoot requirements during load removal, and meeting steady state output ripple voltage requirements. The output capacitor is the most expensive converter component and increases the overall system cost. The output capacitor decoupling in the converter typically includes the low frequency capacitor, such as Specialty Polymer Aluminum, and mid frequency ceramic capacitors. The first purpose of output capacitors is to provide current when the load demand exceeds the inductor current, as shown in Figure 28. Equation 7 shows the charge requirement for a certain load step. The advantage provided by the IR3473 at a load step is the reduced delay compared to a fixed frequency control method. If the load increases right after the PWM signal goes low, the longest delay will be equal to the minimum lower gate on‐time as shown in the Electrical Specifications section. The IR3473 also reduces the inductor current slew time, the time it takes for the inductor current to reach equality with the output current, by increasing the switching frequency up to 1/(T + Min Off Time). This results in ON reduced recovery time. I Load Current Output Charge Inductor Slew Rate Δt Figure 28: Charge Requirement during Load Step ...
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DESIGN EXAMPLE DESIGN CRITERIA Input Voltage, VIN = 6V to 21V Output Voltage, VOUT = 1.25V Switching Frequency, Fs = 400kHz Inductor Ripple Current, 2ΔI = 2A Maximum Output Current, IOUT = 6A Over Current Trip, IOC = 9A Current Transient Step Size = 3A Overshoot Allowance, VOS = VOUT + 50mV Undershoot Allowance, VDROP = 50mV Find R : FF 1.25 V 400k Hz Pick a standard value 158 kΩ, 1% resistor. Find RSET: ...
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STABILITY CONSIDERATIONS Constant‐on‐time control is a fast, ripple based control scheme. Unstable operation can occur if certain conditions are not met. The system instability is usually caused by: Switching noise coupled to FB input: This causes the PWM comparator to trigger prematurely after the 500ns minimum on‐time for lower MOSFET. It will result in double or multiple pulses every switching cycle instead of the expected single pulse. Double pulsing can causes higher output voltage ripple, but in most application it will not affect operation. This can usually be prevented by careful layout of the ground plane and the FB sensing trace. Steady state ripple on FB pin being too small: The PWM comparator in IR3473 requires minimum 7mVp‐p ripple voltage to operate stably. Not enough ripple will result in similar double pulsing issue described above. Solving this may require using output capacitors with higher ESR. ESR loop instability: The stability criteria of constant on‐time is: ESR OUT ON If ESR is too small that this criteria is violated then sub‐ harmonic oscillation will occur. This is similar to the instability problem of peak‐current‐mode control with D>0.5. Increasing ESR is the most effective way to stabilize the system, but the tradeoff is the larger output voltage ripple. System with all ceramic output capacitors: For applications with all ceramic output capacitors, the ESR is usually too small to meet the stability criteria. In these ...
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PCB METAL AND COMPONENT PLACEMENT Lead lands (the 13 IC pins) width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting. Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension. The outboard extension ensures a large toe fillet that can be easily inspected. * Contact International Rectifier to receive an electronic PCB Library file in your preferred format 18 February 16, 2011 | ADVANCED DATASHEET | V1.9 | PD97601 6A Highly Integrated SupIRBuck Pad lands (the 4 big pads) length and width should be equal to maximum part pad length and width. However, the minimum metal to metal spacing should be no less than; 0.17mm for 2 oz. Copper or no less than 0.1mm for 1 oz. Copper or no less than 0.23mm for 3 oz. Copper. Figure 31: Metal and Component Placement IR3473 TM ...
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SOLDER RESIST It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads. The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of 0.05mm to accommodate solder resist misalignment. * Contact International Rectifier to receive an electronic PCB Library file in your preferred format 19 February 16, 2011 | ADVANCED DATASHEET | V1.9 | PD97601 6A Highly Integrated SupIRBuck Ensure that the solder resist in between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. Figure 32: Solder Resist IR3473 TM ...
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STENCIL DESIGN The Stencil apertures for the lead lands should be approximately 80% of the area of the lead lads. Reducing the amount of solder deposited will minimize the occurrences of lead shorts. If too much solder is deposited on the center pad the part will float and the lead lands will open. * Contact International Rectifier to receive an electronic PCB Library file in your preferred format 20 February 16, 2011 | ADVANCED DATASHEET | V1.9 | PD97601 6A Highly Integrated SupIRBuck The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back in order to decrease the risk of shorting the center land to the lead lands when the part is pushed into the solder paste. Figure 33: Stencil Design IR3473 TM ...
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PACKAGE INFORMATION IR WORLD HEADQUARTERS: 21 February 16, 2011 | ADVANCED DATASHEET | V1.9 | PD97601 6A Highly Integrated SupIRBuck Figure 34: Package Dimensions Data and specifications subject to change without notice. This product will be designed and qualified for the Consumer market. Qualification Standards can be found on IR’s Web site. 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 Visit us at www.irf.com for sales contact information. IR3473 TM TAC Fax: (310) 252-7903 www.irf.com ...