IP1827TRPBF International Rectifier, IP1827TRPBF Datasheet
IP1827TRPBF
Specifications of IP1827TRPBF
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IP1827TRPBF Summary of contents
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FEATURES Wide input application 1.5V―16V Single 3.3V or single 5V application Output Voltage Range: 0.6V to 0.75*Vin 0.5% accurate Reference Voltage Programmable Switching Frequency up to 1.5MHz Programmable Soft‐Start Enable input with Voltage Monitoring Capability Remote Sense Amplifier with True Converter Voltage Sensing Thermally compensated Hiccup Mode Over Current Protection Over‐voltage protection Pre‐Bias Start up Body Braking to improve transient Integrated MOSFET drivers and Bootstrap diode Operating temp: ‐40 o C<Tj<125 Thermal Shut Down Power Good Output with Window Comparator Small Size 7.7mmx7.7mm LGA ...
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... PIN 9 PIN 3 EN VCC PIN 14 PIN 10 PGD PGND OCSET PIN 13 PIN 11 PVCC PIN 12 PIN 4 Figure 3: iP1827 Package Bottom View 7.65mm x 7.65mm LGA Tape and Reel Qty 2000 iP1827 Part Number iP1827TRPbF 97599 ...
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FUNCTIONAL BLOCK DIAGRAM EN_CP UVCC VCC Thermal Shutdown Charge Pump LDO PVCC UVPVCC En UVEN Clock Rt & OScillator Ramp 1V Comp Fb Vref E/A 20uA POR 200mV Fault SS Voso Vosm Vosp 3 January 24, 2011 | V1.2 Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator OCP IntVcc Fault SW ...
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TYPICAL APPLICATION DIAGRAM Vin=12V C VCC VCC=3.3V 10uF VCC C PVCC 4.7uF PVCC PGood PGD 36 0.1 uF BiasGnd LGnd Figure 5: iP1827 Application Circuit Diagram for a 12V to 1.8V, 25A Point of Load Converter 4 January 24, 2011 | V1.2 Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator 49.9 K ...
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PIN DESCRIPTIONS PIN # PIN NAME 1 VIN 2 SW 3 PGND 4 PVCC 5 SS 6 LGND 7 VOSM 8 VOSP 9 RT 10 VCC 11 OCSET 12 BIASGND 13 PGD 14 EN 15 VOSO 16 COMP 17 FB ...
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ABSOLUTE MAXIMUM RATINGS VIN VCC PVCC SW BOOT Input/output pins, except PGD, Vosp and Voso PGD, Vosp and Voso PGND to LGND, BIASGND to LGND, Vosm to LGND Storage Temperature Range Junction Temperature Range ESD Classification Moisture Sensitivity level Note 1: Must not exceed 8V. Note 2: PVCC must not exceed 7.5V for Junction Temperature between ‐10°C and ‐40°C. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. These devices are ESD sensitive, observe handling precautions to prevent electrostatic discharge damage. 6 January 24, 2011 | V1.2 Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator ‐0.3V to 25V ‐0.3V to 3.9V ‐0.3V to 8V (Note 2) ‐0.3V to 25V (DC), ‐4V to 25V (AC, 100ns) ‐0.3V to 33V ‐0.3V to VCC + 0.3V ‐0.3V to PVCC + 0.3V (Note 2) ‐0.3V to + 0.3V ‐55°C to 150°C ‐40°C to 150°C JEDEC Class 1C (1KV) JEDEC Level 3@250°C iP1827 97599 ...
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ELECTRICAL SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS SYMBOL VIN Input Voltage PVCC Supply Voltage VCC Supply Voltage Boot to SW Supply Voltage V Output Voltage Output Current O Fs Switching Frequency T Junction Temperature J ELECTRICAL CHARACTERISTICS Unless otherwise specified, these specification apply over, 1.5V < Vin < 16V, 3.13V < Vcc < 3.46V. 0 o Typical values are specified at T = 25 A PARAMETER Power Loss Power Loss P LOSS MOSFET R ...
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PARAMETER SYMBOL VCC – Start – Threshold VCC_UVLO_Start VCC – Stop – Threshold VCC_UVLO_Stop Enable – Start – Threshold Enable_UVLO_Start Enable – Stop – Threshold Enable_UVLO_Stop Oscillator Rt Voltage Frequency Range F S Ramp Offset Ramp (os) Min Pulse Width Dmin (ctrl) Fixed Off Time Max Duty Cycle Dmax Error Amplifier Input Bias Current IFb(E/A) Input Bias Current IVp(E/A) Sink Current Isink(E/A) Source Current Isource(E/A) Slew Rate SR Gain‐Bandwidth Product GBWP DC Gain ...
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PARAMETER Shutdown Output SD Threshold Bootstrap Diode Forward Voltage Switch Node SW Leakage Current lsw Charge Pump (PVCC) Output Voltage PVCC Oscillator Frequency Fs_CP Body Braking BB Threshold BB_threshold Power Good Power Good Lower VPG (lower) Threshold Lower Threshold Delay VPG (lower)_Dly PGood Voltage Low PG (voltage) Leakage Current I LEAKAGE Over Voltage Protection (OVP) OVP Trip Threshold OVP (trip) OVP Fault Prop Delay OVP (delay) Over‐Current Protection OC Trip Current I TRIP SS Off Time ...
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TYPICAL OPERATING CHARACTERISTICS (‐40°C ‐ 125°C) Icc (Standby) 600 560 520 480 440 400 360 320 280 240 200 -40 - Temp (Standby) PVcc 200 180 160 140 120 100 -40 - ...
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TYPICAL OPERATING CHARACTERISTICS (‐40°C ‐ 125°C) VCC_UVLO_Start 3.1 3.05 3 2.95 2.9 2.85 2.8 2.75 2.7 2.65 2.6 -40 - Temp [ C] PVCC_UVLO_Start 4.4 4.36 4.32 4.28 4.24 4.2 4.16 4.12 4.08 4.04 4 -40 - ...
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TYPICAL OPERATING CHARACTERISTICS (‐40°C ‐ 125°C) R DSON 6 5.75 5.5 5.25 5 4.75 4.5 4.25 4 3.75 3.5 -40 -20 2.7 2.5 2.3 2.1 1.9 1.7 1.5 1.3 -40 -20 12 January 24, 2011 | V1.2 Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator of Control FET over temperature at PVCC=5V 0 ...
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THEORY OF OPERATION INTRODUCTION The iP1827 uses a PWM voltage mode control scheme with external compensation to provide good noise immunity and maximum flexibility in selecting inductor values and capacitor types. The switching frequency is programmable from 250kHz to 1.5MHz and provides the capability of optimizing the design in terms of size and performance. iP1827 provides precisely regulated output voltage programmed from 0.6V to 0.75*Vin using two external resistors. The iP1827 is capable of operating with either a 3.3V Vcc bias voltage (3.13V to 3.46V) or a PVcc bias voltage from 4.5V to 7.5V, allowing an extended operating input voltage range from 1.5V to 16V. The device utilizes the on‐resistance of the low side MOSFET as the current sense element; this method enhances the converter’s efficiency and reduces cost by eliminating the need for external current sense resistor. iP1827 includes two low R MOSFETs using IR’s HEXFET ds(on) technology. These are specifically designed for high efficiency applications. BIASING THE IP1827 The iP1827 offers flexibility in choosing the bias supply voltage as it is capable of operating with a 5V bias voltage as well as a 3.3V bias voltage (Figure 1 and Figure 32) If it is preferred to use a 5V bias voltage, this should be applied between the PVcc pin and the local bias PGnd (pin 12), with the Vcc pin tied to the local bias PGnd also. 6.5 6.45 6.4 6.35 6.3 6.25 6.2 6.15 ...
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Bus Voltage (12V ) 10 nable Threshold = 1.2V Figure 7a: Normal Start up, Device turns on when the Bus voltage reaches 10.2V Bus Voltage (12V) PVcc(5V) or Vcc(3.3V) Figure 7b: Recommended startup sequence with Vcc or PVcc PRE‐BIAS STARTUP iP1827 is able to start up into pre‐charged output, which prevents oscillation and disturbances of the output voltage. The output starts in asynchronous fashion and keeps the synchronous MOSFET off until the first gate signal for control MOSFET is generated, following which, the synchronous MOSFET starts with a narrow duty cycle of 12.5% and gradually increases its duty cycle in steps of 12.5%, with 32 cycles at each step until the end of pre‐bias. 14 January 24, 2011 | V1.2 Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator ...
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POR 0.8V 0.2V Vss Vout Figure 10: Theoretical operation waveforms during soft‐start OPERATING FREQUENCY The switching frequency can be programmed between 250kHz – 1500kHz by connecting an external resistor from R pin to Gnd. Table 1 tabulates the oscillator frequency T versus R . ABLE WITCHING REQUENCY VS XTERNAL Fsw (kHz) R (kohm) T 250 88.7 300 73.2 400 54.9 ...
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An overcorrect detection trips the OCP comparator, latches OCP signal and cycles the soft start function in hiccup mode. The hiccup is performed by shorting the soft‐start capacitor to ground and counting the number of switching cycles. The Soft Start pin is held low until 4096 cycles have been completed. Following this, the OCP signal resets and the converter recovers. After every soft start cycle, the converter stays in this mode until the overload or short circuit is removed. For the iP1827, the Sync FET is turned OFF on the falling edge of a PWMSet or Clock signal that has duration of 25% of the switching period. For operation at the maximum duty cycle, the OCP circuit samples current for 40 ns, starting 40 ns after the low drive signal for the Sync FET > 70% of PVcc. ABLE VERCURRENT SETTING VS XTERNAL I (A) External Rocset (kohm) otrip 15 2.61 16 2.94 17 3.24 18 3.65 19 4.02 20 ...
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In applications where only local sensing is required for feedback, the remote voltage sensing pins of the iP1827 may be dedicated to sensing the output for power good indication and overvoltage protection. POWER GOOD OUTPUT AND OVER‐VOLTAGE PROTECTION The IC continually monitors the output voltage via output of the remote sense amplifier (Voso pin). The Voso voltage forms an input to a window comparator whose upper and lower thresholds are 0.7V and 0.51V respectively. Hence, the Power Good signal is flagged when the Voso pin voltage is within PGood window, i.e., between 0.51V and 0.69V, as shown in Figure 12a. The PGood pin is open drain and it needs to be externally pulled high. High state indicates that output is in regulation. Figure 12a also shows the PGood timing diagram with a 256 cycle delay between the Voso voltage entering within the thresholds defined by the PGood window and PGood going high If the output voltage exceeds the over voltage threshold 0.7V, an over voltage trip signal is asserted; this will turn off the high side driver and turn on the low side driver until the Voso voltage drops below the 0.7V threshold. Both drivers are then turned off until a reset is performed by cycling Vcc (or PVcc/Enable) or until another OVP event occurs turning on the low side driver again. Figure 12b shows the response in over‐voltage condition. 0.8V 0. Voso 0.51V 0 PGD 0 256/Fs 256/Fs Figure 12a: iP1827 Power Good Signal Timing Diagram 17 January 24, 2011 | V1.2 ...
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MINIMUM ON TIME CONSIDERATIONS The minimum ON time is the shortest amount of time for which the Control FET may be reliably turned on, and this depends on the internal timing delays. For the iP1827, the minimum on‐time is specified as 50 ns maximum. Any design or application using the iP1827 must require a pulse width that is at least equal to this minimum on‐time and preferably higher than 100 ns. This is necessary for the circuit to operate without jitter and pulse‐skipping, which can cause high inductor current ripple and high output voltage ripple. MAXIMUM DUTY RATIO CONSIDERATIONS For the iP1827, the upper limit on the operating duty ratio is set by the duration of the PWMSet pulse or by the 200 ns fixed off‐time, whichever is higher. Since the PWMSet pulse has a 25% duty cycle, this limits the maximum duty ratio at which the iP1827 can operate, to 75%. At switching frequencies above 1.25 MHz, however, the maximum duty ratio is set by the 200 ns fixed off‐time. Thus, at switching frequencies above 1.25 MHz, higher the switching frequency, the lower is the maximum duty ratio at which the iP1827 can operate. Figure 13 shows a plot of the maximum duty ratio v/s the switching frequency, with 200 ns off‐time. 76% 75% 74% 73% 72% 71% 70% 69% 68% 67% 66% 250 350 450 550 650 ...
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DESIGN PROCEDURE APPLICATION INFORMATION Design Example The following example is a typical application for iP1827. The application circuit is shown on page 1. V = 12V (13.2V max) = 1.8V = 25A o ΔV (transient) ≤ ±90mV for ΔIo = 10.5A @ 2.5A/µs o ΔV (ripple) ≤ ±13.5mV (±0.75%) o F = 600kHz s ENABLING THE IP1827 As explained earlier, the precise threshold of the Enable lends itself well to implementation of a UVLO for the Bus Voltage. iP 1827 Enable For a typical Enable threshold of V = 1.2 V ...
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For our design, R is selected to be 604 ohm. bot This selection is based on a trade‐off between two considerations: 1) The resistive divider should be as low impedance as possible in order to have minimal impact on the impedance seen at the Vosp and Vosm pins. 2) The resistive divider should have high enough impedance so as to minimize the bleed current from the output. Hence, from Equation (9), R = 1.21K. top In order to ensure that the Vosp and Vosm see balanced impedances, it is advisable to use R comp 402 Ω comp top bot SOFT‐START PROGRAMMING The soft‐start timing can be programmed by selecting the soft‐start capacitance value. From (1), for a desired start‐ up time of the converter, the soft start capacitor can be calculated by using: ...
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OUTPUT CAPACITOR SELECTION The voltage ripple and transient requirements determine the output capacitors type and values. The criteria are normally based on the value of the Effective Series Resistance (ESR). However the actual capacitance value and the Equivalent Series Inductance (ESL) are other contributing components. These components can be described as: ESR ) o ( ESL ) ESR o ...
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V Z OSO E REF Gain(dB) H( Figure 18: Type II compensation network and its asymptotic gain plot The transfer function (V /V ) is given by: e oso Z ...
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By replacing Z and Z according to Figure 19, the transfer in f function can be expressed as: C ...
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These result in: F =26.53kHz =4.4MHz ESR F /2=300kHz s Select crossover frequency F =110 kHz o Since F <F <F /2<F , Type III is selected to place ESR the pole and zeros. Detailed calculation of compensation Type III: Desired Phase Margin Θ = 80° 1 sin 9.62 kHz ...
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TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vcc=3.3V, Vo=1.8V, Io=0A ‐ 25A, Room Temperature, no airflow Figure 20: Start up at 25A Load , Ch :V , Ch :V , Figure 22 : Start up with 1V Pre Bias , 0A Load, Ch Figure 24 : Inductor node at 25A load Ch :LX 2 25 January 24, 2011 | V1.2 Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator :Enable 4 :V , Ch :V Figure 23: Output Voltage Ripple, 25A load ...
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TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vcc=3.3V, Vo=1.8V, Io=3.5A ‐ 14A, Room Temperature, no airflow Figure 26: Transient Response, 3.5A to 14A step (2.5A/us) 26 January 24, 2011 | V1.2 Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator 2 out iP1827 97599 ...
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TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vcc=3.3V, Vo=1.8V, Io=3.5A ‐ 14A, Room Temperature, no airflow Figure 27: Transient Response, 24.5A to 25A step (2.5A/us) 27 January 24, 2011 | V1.2 Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator out iP1827 97599 ...
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TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vcc=3.3V, Vo=1.8V, Io=0A ‐ 25A, Room Temperature Figure 28: Bode Plot at 25A load shows a bandwidth of 110.88kHz and phase margin of 51.29 degrees 28 January 24, 2011 | V1.2 Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator iP1827 97599 ...
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TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vcc=3.3V, Vo=1.8V, Io=0A ‐ 25A, Room Temperature, No airflow 2 4.5 4 3.5 3 2.5 2 1.5 1 0 January 24, 2011 | V1.2 Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator 7.5 10 12.5 15 17.5 Iout (A) ...
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THERMAL IMAGES Vin=12.0V, Vcc=3.3V, Vo=1.8V, Io=0A‐25A, Room Temperature, 200 LFM 30 January 24, 2011 | V1.2 Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator Figure 31: Thermal Image of the board at 25A load Test point 1 is iP1827 Test point 2 is inductor iP1827 97599 ...
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OTHER APPLICATION CIRCUITS 31 January 24, 2011 | V1.2 Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator Figure 32: Application with external PVCC=5V Figure 33: Single 5V application iP1827 97599 ...
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Vin=3.3V PVCC PGood PGD Rt SS LGnd BiasGnd 32 January 24, 2011 | V1.2 Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator Vin VCC En OCSet SW Vosp Vosm Voso Fb Comp PGnd Figure 34: Single 3.3V Application iP1827 Vo 97599 ...
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LAYOUT CONSIDERATIONS The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Make all the connections for the power components in the top layer with wide, copper filled areas or polygons. In general, it is desirable to make proper use of power planes and polygons for power distribution and heat dissipation. The inductor, output capacitors and the iP1827 should be as close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. The input capacitors should be placed as close as possible to the PGnd pad. The connection of the Vin pad to the Vin power polygon should be low impedance, using several vias in parallel. The layout must ensure minimum length ground path and enough copper for input and output capacitors with a direct connection. The iP1827 has a local power ground pad called Bias Gnd (pin 12) for bypassing Vcc or PVcc supplies. The analog or signal ground, LGnd, is used as a separate control circuit ground to which all signals are referenced. The analog Enough copper & minimum length ground path between Input and Output All bypass caps (Marked in Cyan) should be placed as close as possible to their connecting pins BiasGnd Single Point Connection of AGND and BiasGnd Resistors Rt (marked in Brown) should be placed as close as possible to their pins Compensation parts (Marked in dark blue) ...
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LGND Figure 35b: IRDC1827 demoboard layout considerations – Bottom Layer GND PGND AGND Figure 35c: IRDC1827 demoboard layout considerations – Mid Layer 1 SW PGND Figure 35e: IRDC1827 demoboard layout considerations – Mid Layer 3 34 January 24, 2011 | V1.2 Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator VOUT PGND Vin Vin PGnd GND SW AGnd Vin PGND Vout Vin Figure 35d: IRDC1827 demoboard layout considerations – GND Figure 35f: IRDC1827 demoboard layout considerations – iP1827 Remote sense traces, tapped at a low impedance node, such as across a capacitor, shielded by PGND layer are routed very close to each other ...
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METAL AND COMPONENT PLACEMENT * Contact International Rectifier to receive an electronic PCB Library file in your preferred format. 35 January 24, 2011 | V1.2 Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator Figure 36: PCB Metal and Component Placement iP1827 97599 ...
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SOLDER RESIST It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads. The three power land pads should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of 0.05mm to accommodate solder resist mis‐alignment. * Contact International Rectifier to receive an electronic PCB Library file in your preferred format. 36 January 24, 2011 | V1.2 Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator Ensure that the solder resist in‐between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the power pad lands. Figure 37: Solder resist iP1827 97599 ...
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STENCIL DESIGN The Stencil apertures for the lead lands should be approximately 80% of the area of the lead pads. Reducing the amount of solder deposited will minimize the occurrences of lead shorts. If too much solder is deposited on the three power land pads the part will float and the lead pads will be open. * Contact International Rectifier to receive an electronic PCB Library file in your preferred format. 37 January 24, 2011 | V1.2 Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator The maximum length and width of the power land pads stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of opens to the lead lands or use the recommended stencil design below. Figure 38: Stencil design iP1827 97599 ...
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MARKING INFORMATION A1 Marking Date Code Assembly Lot Code Part Number PACKAGE INFORMATION 38 January 24, 2011 | V1.2 Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator International Rectifier Logo YYWW xxxxxx 1827PBF CS Factory Code Figure 39: Marking Information Figure 40: Tape and Reel Information iP1827 97599 ...
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Highly Integrated 25A Single‐input Voltage, 7.650 [0.301] 0.15 [.006 CORNER ID TOP VIEW 7.32 3.62 2.41 1.35 0.28 0.36 1.21 1.43 2.05 2.49 3.56 3.86 4.63 4.71 5.69 6.76 7.27 Figure 41: Mechanical Outline Drawing IR WORLD HEADQUARTERS: 39 January 24, 2011 | V1.2 Synchronous Buck Regulator B ...