IP1837TRPBF International Rectifier, IP1837TRPBF Datasheet - Page 14

• Manufacturer Part Number: IP1837TRPBF
• Description: IC DC-DC REG SYNC BUCK LGA
• Manufacturer: International Rectifier
• Series: iPOWIR™r
• Type: Step-Down (Buck), PWM - Voltage Moder

Specifications of IP1837TRPBF

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.6 V ~ 12 V
• Current - Output: 35A
• Frequency - Switching: 250kHz ~ 1.5MHz
• Voltage - Input: 1.5 V ~ 16 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: *
• Package / Case: *
• Package: LGA - 7.7 x 7.7
• Circuit: Single Output
• Iout (a): 35
• Switch Freq (khz): 250 - 1500
• Input Range (v): 1.5 - 16
• Output Range (v): 0.6 - 0.75*Vin
• Internal Bias Ldo: Yes
• Ocp Otp Uvlo Pre-bias Soft Start And: Remote Sense + Body Tracking + Temp Comp OCP
• Pbf: PbF Option Available
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

THEORY OF OPERATION
INTRODUCTION
The iP1837 uses a PWM voltage mode control scheme with
external compensation to provide good noise immunity
and maximum flexibility in selecting inductor values and
capacitor types.
The switching frequency is programmable from 250kHz
to 1.5MHz and provides the capability of optimizing the
design in terms of size and performance.
iP1837 provides precisely regulated output voltage
programmed from 0.6V to 0.75*Vin using two external
resistors. The iP1837 is capable of operating with either
a 3.3V Vcc bias voltage (3.13V to 3.46V) or a PVcc bias
voltage from 4.5V to 7.5V, allowing an extended operating
input voltage range from 1.5V to 16V.
The device utilizes the on‐resistance of the low side
MOSFET as the current sense element; this method
enhances the converter’s efficiency and reduces cost by
eliminating the need for external current sense resistor.
iP1837 includes two low R
technology. These are specifically designed for high
efficiency applications.
BIASING THE IP1837
The iP1837 offers flexibility in choosing the bias supply
voltage as it is capable of operating with a 5V bias voltage
as well as a 3.3V bias voltage (Figure 1 and Figure 32) If it is
preferred to use a 5V bias voltage, this should be applied
between the PVcc pin and the local bias PGnd (pin 12),
with the Vcc pin tied to the local bias PGnd also.
Figure 6: PVcc v/s Switching Frequency (Fsw) with Vcc=3.3V
6.45
6.35
6.25
6.15
6.05
5.95
6.5
6.4
6.3
6.2
6.1
6
200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500
14
March 3, 2011 | V1.24
ds(on)
Fsw (kHz)
MOSFETs using IR’s HEXFET
Highly Integrated 35A Single‐input Voltage,
Synchronous Buck Regulator
Alternatively, if operation from 3.3V bias is desired, the
3.3V supply should be applied between Vcc and the local
bias PGnd. An internal charge‐pump whose output is tied
to PVcc, roughly doubles this Vcc voltage. This should be
preferred for high current applications which may benefit
from the lower Rds(on) on account of the higher PVcc
(almost 6.3V, from Figure 6), which forms the supply to the
gate drivers.
UNDER‐VOLTAGE LOCKOUT AND POR
The under‐voltage lockout circuit monitors the input
supply PVcc and the Enable input. It ensures that the
MOSFET driver outputs remain in the off state whenever
either of these two signals drop below the set thresholds.
Normal operation resumes once PVcc and Enable rise
above their thresholds.
The POR (Power On Ready) signal is generated when all
these signals reach the valid logic level (see system block
diagram). When the POR is asserted the soft start
sequence starts (see soft start section).
ENABLE
The Enable feature allows another level of flexibility for
start up. The Enable has precise threshold which is
internally monitored by Under‐Voltage Lockout (UVLO)
circuit. Therefore, the iP1837 will turn on only when the
voltage at the Enable pin exceeds this threshold, typically,
1.2V
If the input to the Enable pin is derived from the bus
voltage by a suitably programmed resistive divider, it can
be ensured that the iP1837 does not turn on until the bus
voltage reaches the desired level. Only after the bus
voltage reaches or exceeds this level will the voltage at
Enable pin exceed its threshold, thus enabling the iP1837.
Therefore, in addition to being a logic input pin to enable
the iP1837, the Enable feature, with its precise threshold,
also allows the user to implement an Under‐Voltage
Lockout for the bus voltage V
for high output voltage applications, where we might want
the iP1837 to be disabled at least until V
desired output voltage level.
Figure 7a shows the startup sequence with the Enable
used to implement a precise under‐voltage lockout for V
Figure 7b. shows the recommended start‐up sequence for
iP1837, when Enable is used as a logic input.
in
. This is desirable particularly
in
iP1837
exceeds the
97600
in
.