LM5072EVAL/NOPB National Semiconductor, LM5072EVAL/NOPB Datasheet - Page 13

• Manufacturer Part Number: LM5072EVAL/NOPB
• Description: EVAL BOARD FOR LM5072
• Manufacturer: National Semiconductor

Specifications of LM5072EVAL/NOPB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

operated at elevated ambient temperatures and the classifi-
cation time exceeds the IEEE802.3af limit of 75 ms.
When the classification option is not required, simply leave
the RCLASS pin open to set the PD to the default Class 0
state. Class 0 requires that the PSE allocate the maximum
IEEE802.3af specified power of 15.4 W (12.95 W at the PD
input terminals) to the PD.
Undervoltage Lockout (UVLO)
The LM5072’s internal preset UVLO circuit continuously mon-
itors the PoE input voltage between the VIN and VEE pins.
Figure 6 illustrates the block diagram of the LM5072 UVLO
circuit. This function requires no external components. The
UVLO signal can be over-ridden by the front auxiliary power
option (see details in the FAUX section) to allow the hot swap
MOSFET of the LM5072 to pass power from front auxiliary
power sources at voltage levels below the PoE operating volt-
age. In the rear auxiliary power application (see RAUX sec-
tion), the auxiliary power source bypasses the hot swap
MOSFET and is applied directly to the input of the DC-DC
converter. The UVLO function does not need to be over-rid-
den in this configuration.
The PD can draw a maximum current of 400 mA during stan-
dard 802.3af PoE operation. This current will cause a voltage
drop of up to 8V over a 100m long Ethernet cable. The PD
front-end current steering diode bridges may introduce an ad-
ditional 2V drop. In order to guarantee successful startup at
the minimum PoE voltage of 42V, and to continue operation
at the minimum requirement of 36V as specified by IEEE
802.3af, these voltage drops must be taken into account.
FIGURE 6. Preset Input UVLO Function
13
When the V
circuit will release the hot swap MOSFET and initiate the
startup inrush sequence. When the V
31V nominal during normal operating mode, the LM5072 dis-
ables the PD by shutting off the hot swap MOSFET.
Therefore, the LM5072 UVLO thresholds have been set to
38V on the rising edge of VIN, and 31V on the falling edge of
VIN. The 7V nominal hysteresis of the UVLO function, in ad-
dition to the inrush current limit (discussed in the next section),
prevents false starts and chattering during startup.
Inrush Current Limit Programming
According to IEEE 802.3af, the input capacitance of the PD
power supply must be at least 5 µF (between the VIN and RTN
pins). Considering the capacitor tolerance and the effects of
voltage and temperature, a nominal capacitor value of at least
10 µF is recommended to ensure 5 µF minimum under all
conditions. A greater amount of capacitance may be needed
to filter the input ripple of the DC-DC converter. The input ca-
pacitors remain discharged during detection and classifica-
tion modes of the PD interface. The hot swap MOSFET is
turned on after the VIN minus VEE voltage difference rises
above the UVLO release threshold of 38V nominal. When
enabled, the hot swap MOSFET delivers a regulated inrush
IN
voltage rises above 38V nominal, the UVLO
20184620
IN
voltage falls below
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