NCP3127AGEVB ON Semiconductor, NCP3127AGEVB Datasheet - Page 8

• Manufacturer Part Number: NCP3127AGEVB
• Description: BOARD EVAL NCP3127
• Manufacturer: ON Semiconductor

Specifications of NCP3127AGEVB

• Design Resources: NCP3127AGEVB Schematic
• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Power - Output: -
• Voltage - Output: Adj down to 0.8V
• Current - Output: 2A
• Voltage - Input: 4.5 ~ 13.2 V
• Regulator Topology: Buck
• Frequency - Switching: 350kHz
• Board Type: Fully Populated
• Utilized Ic / Part: NCP3127A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

source of 10 mA (typ), which charges the external integrator
capacitor of the OTA. Figure 14 is a typical soft−start
sequence. The sequence begins once V
their UVLO thresholds and OCP programming is complete.
The current sourced out of the COMP pin continually
increases the voltage until regulation is reached. Once the
voltage reaches 400 mV logic is enabled. When the voltage
exceeds 900 mV, switching begins. Current is sourced out of
the COMP pin, placing the regulator into open loop
operation until 800 mV is sensed at the FB pin. Once
800 mV is sensed at the FB pin, open loop operation ends
and closed loop operation begins. In closed loop operation,
the OTA is capable of sourcing and sinking 120 mA.
Overcurrent Threshold Setting
550 mV, by adding a resistor (R
GND. During a short period of time following V
over UVLO threshold, an internal 10 mA current (I
sourced from the ISET pin, creating a voltage drop across
R
internal voltage ramp. Once the internal stepped voltage
reaches the R
power is cycled. The overall time length for the OC setting
procedure is approximately 9 ms. Connecting an R
resistor between ISET and GND, the programmed threshold
will be:
BG Comparator
BG Comparator Output
COMP
SET
NCP3127 overcurrent threshold can be set from 50 mV to
DAC Voltage
I
VCC
OCth
VFB
Vout
BG
TG
. The voltage drop is compared against a stepped
UVLO
+
4.2 V
I
OCSET
Delay
POR
Figure 18. Soft−Start Sequence
SET
R
DS(on)
Trip Set
Current
50 mV
voltage, the value is stored internally until
* R
SET
COMP
Delay
500 mV
0.9 V
³ 2.0 A +
Soft−Start Normal Operation
SET
10 mA * 21 kW
) between ISET and
IN
105 mW
and V
BST
3.85 V
OCSET
UVLO
IN
surpass
(eq. 1)
http://onsemi.com
rising
SET
) is
8
I
I
R
R
connected, the device switches the OCP threshold to a fixed
375 mV value (3.57 A), an internal safety clamp on ISET is
triggered as soon as ISET voltage reaches 700 mV, enabling
the 375 mV fixed threshold and ending the OCP setting
period. The current trip threshold tolerance is $25 mV. The
accuracy is best at the highest set point (550 mV). The
accuracy will decrease as the set point decreases.
will vary the over current set threshold operating point. A
graph of the typical current limit set thresholds at 4.5 V and
12 V is shown in Figure 19.
Current Limit Protection
conduct large currents. The regulator will latch off,
protecting the load and MOSFETs from excessive heat and
damage. Low−side R
of each LS−FET turn−on duration to sense the current.
While the low side MOSFET is on, the V
compared to the user set internally generated OCP trip
voltage. If the V
an overcurrent condition occurs and a counter counts
consecutive current trips. If the counter reaches 7, the PWM
logic and both HS−FET and LS−FET are turned off. The
regulator has to go through a Power On Reset (POR) cycle
to reset the OCP fault as shown in Figure 20.
OCSET
OCth
DS(on)
SET
The R
MOSFET tolerances with temperature and input voltage
In case of an overload, the low−side (LS) FET will
3.5
2.5
1.5
0.5
4
3
2
1
0
5
= Current trip threshold
= Current set resistor
= Sourced current
= On resistance of the low side MOSFET
SET
Figure 19. R
values range from 5 kW to 55 kW. If R
12 V
10
SW
voltage is lower than OCP trip voltage,
DS(on)
SET
5.0 V
15
R
Value for Output Current
sense is implemented at the end
SET
(kW)
20
SW
25
voltage is
SET
is not
30