DS99R124Q-EVK/NOPB National Semiconductor, DS99R124Q-EVK/NOPB Datasheet - Page 15

• Manufacturer Part Number: DS99R124Q-EVK/NOPB
• Description: EVAL BOARD FOR DS99R124Q
• Manufacturer: National Semiconductor

Specifications of DS99R124Q-EVK/NOPB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

If there is a loss of clock from the input serial stream, LOCK
is driven Low and the state of the outputs are based on the
OSS_SEL setting (configuration pin or register).
LVCMOS 1.8V / 3.3V VDDIO Operation
The LVCMOS inputs and outputs can operate with 1.8 V or
3.3 V levels (V
V levels will offer a lower noise (EMI) and also a system power
savings.
FPD-LINK OUTPUT
VODSEL
The differential output voltage of the FPD-Link interface is
controlled by the VODSEL input.
VODSEL
H
PDB
L
H
H
H
H
H
H
L
L
TABLE 2. VODSEL Configuration Table
DDIO
Result
VOD is 250mV TYP (500mVp-p)
VOD is 400mV TYP (800mVp-p)
) for target (Display) compatibility. The 1.8
INPUTS
OEN
H
H
H
X
X
L
L
L
OSS_SEL
H
H
H
L
L
L
X
X
TABLE 1. Output State Table
LOCK
Z
H
H
L
L
L
L
L
15
OTHER OUTPUTS
TxCLKOUT is TRI-STATE
TxOUT[2:0] areTRI-STATE
OS[2:0] are TRI-STATE
PASS is TRI-STATE
TxCLKOUT is TRI-STATE
TxOUT[2:0] areTRI-STATE
OS[2:0] are LOW
PASS is TRI-STATE
TxCLKOUT is TRI-STATE
TxOUT[2:0] areTRI-STATE
OS[2:0] are LOW
PASS is HIGH
TxCLKOUT is TRI-STATE
TxOUT[2:0] areTRI-STATE
OS[2:0] are LOW
PASS is LOW
TxCLKOUT is TRI-STATE
TxOUT[2:0] areTRI-STATE
OS[2:0] are TRI-STATE
PASS is HIGH
TxCLKOUT is TRI-STATE
TxOUT[2:0] areLOW
OS[2:0] are LOW
PASS is LOW
TxCLKOUT is TRI-STATE
TxOUT[2:0] areTRI-STATE
OS[2:0] are Active
PASS is Active
(This setting allows the system to run BIST or use the OS[2:0]
bits while the panel is off)
TxCLKOUT is Active
TxOUT[2:0] are Active
OS[2:0] are Active
PASS is Active
(Normal operating mode)
SSCG Generation — Optional
The Des provides an internally generated spread spectrum
clock (SSCG) to modulate its outputs. Both clock and data
outputs are modulated. This will aid to lower system EMI.
Output SSCG deviations to ±2.0% (4% total) at up to 35kHz
modulations nominally are available. See
4. This feature may be controlled by pins or by register. The
LFMODE should be set appropriately if the SSCG is being
used. Set LFMODE High if the clock frequency is between 5
MHz and 20 MHz, set LFMODE Low if the clock frequency is
between 20 MHz and 43 MHz.
OUTPUTS
Table 3
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and
Table