MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 981

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
30
Revision history
Table 215. Document revision history
19-Oct-2007
Date
Revision
1
Document reference number changed from UM0306 to RM008. The
changes below were made with reference to revision 1 of 01-Jun-2007 of
UM0306.
EXTSEL[2:0] and JEXTSEL[2:0] removed from
page 201
Notes added to
Section 11.9.7 on page 215
SPI_CR2 corrected to SPI_CR1 in
page
f
on page
Section 23.3.6: CRC calculation on page 595
communication using DMA (direct memory addressing) on page 596
modified.
Note added to bit 13 description changed in
register 1 (SPI_CR1) (not used in I
modified in
On 64-pin packages on page 54
Section 8.3.2: Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1 on
page 152
Description of SRAM at address 0x4000 6000 modified in
map on page 39
Note added to
Section 22.2: bxCAN main features on page
Figure 4: Power supply overview
modified.
Formula added to Bits 25:24 description in
(CAN_BTR) on page
Section 10.3: DMA functional description on page 183
Example of configuration on page 970
MODEx[1:0] bit definitions corrected in
register high (GPIOx_CRH) (x=A..G) on page
Downcounting mode on page 260
Figure 80: Output stage of capture/compare channel (channel 4) on
page 271
OCx output enable conditions modified in
page
Section 13.3.19: TIMx and external trigger synchronization on page 290
changed.
CC1S, CC2S, CC3S and CC4S definitions modified for (1, 1) bit setting
modified in
(TIMx_CCMR1)
register 2
CC1S, CC2S, CC3S and CC4S definitions for (1, 1) bit setting modified in
Section 14.4.7: TIMx capture/compare mode register 1 (TIMx_CCMR1)
Section 14.4.8: Capture/compare mode register 2
AFIO_EVCR pins modified in
on page
CPU
frequency changed to f
594.
275.
Doc ID 13902 Rev 9
587.
167.
and V
updated.
and
(TIMx_CCMR2).
Section 23.5.3: SPI status register (SPI_SR) on page
Section 13.4.7: TIM1&TIM8 capture/compare mode register 1
Section 13.3.6: Input capture mode on page 271
Figure 82: Output compare mode, toggle on OC1.
Section 21.2: USB main features on page 512
REF+
Section 11.3.9 on page
and
and
Section 13.4.8: TIM1&TIM8 capture/compare mode
range modified in Remarks column.
Table 1: Register boundary
571.
PCLK
and
Table 51: AFIO register map and reset values
Section 11.9.9 on page
modified.
and
Changes
in
modified.
2
1 clock and 1 bidirectional data wire on
Section 23.2: SPI and I
S mode) on page
On 100-pin and 144- pin packages
modified.
Section 8.2.2: Port configuration
204,
Section 13.3.10: PWM mode on
CAN bit timing register
Section 23.5.1: SPI control
542.
Section 11.9.2 on page
and
149.
Table 60: ADC pins on
addresses.
Section 23.3.7: SPI
(TIMx_CCMR2).
614. Note for bit 4
modified.
216.
Revision history
Figure 2: Memory
2
S main features
and
modified.
modified.
617.
981/995
212,
and
title