1323XNSK Freescale Semiconductor, 1323XNSK Datasheet - Page 9

• Manufacturer Part Number: 1323XNSK
• Description: KIT DEV FOR 1323X_NETWORK
• Manufacturer: Freescale Semiconductor
• Type: Transceiver, 802.15.4r

Specifications of 1323XNSK

• Frequency: 2.4GHz
• Interface Type: SPI
• For Use With/related Products: MC1323x
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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The MC1323x provides a unique Partial Power Down receive (PPD_RX) mode. When this mode is
selected:
Use of the PPD_RX mode provides two distinct advantages:
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The onboard CPU is a 32 MHz 8-bit HCS08 core. It executes a super set of the 68HC08 instruction set
with added BGND instructions. The HCS08 CPU is fully source and object code compatible with the
M68HC08 CPU. Several instructions and enhanced addressing modes are added to improve C compiler
efficiency and to support a new background debug system. It has an 8-bit data bus, a 16-bit address bus
and a 2-stage instruction pipe that facilitates the overlapping of instruction fetching and execution. There
are 29 vectors for internal interrupt sources and one vector for an external interrupt pin. The debug or BDM
module provides a serial one-wire interface for non-intrusive debugging of application programs.
Features of the HCS08 CPU include:
Freescale Semiconductor
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1. Reduced “listen” mode current - The receive current is significantly reduced while waiting for a
2. Reduced sensitivity as a desired effect - The PPD_RX mode provides different levels of reduced
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Whenever a receive cycle is initiated, the receiver is not turned fully on to save current until receive
energy of a preset level is detected
The receiver will turn fully on only when triggered by energy at the preset level, and then receives
the expected frame. The full-on state is the same as the standard receive state
The preset level can be programmed for various RX input power levels
frame. If a node is a coordinator, router, or gateway and it spends a significant percentage of its
RF-active time waiting for incoming frames from clients or other devices, the net power savings
can be significant.
sensitivity. If a node operates in a densely populated area, it may be desirable to de-sensitize the
receiver such that the device does not respond to incoming frames with an energy level below the
desired threshold. This could be useful for security, net efficiency, reduced noise triggering and
many other purposes.
HCS08 8-Bit Central Processing Unit (CPU)
Object code fully upward-compatible with M68HC05 and M68HC08 Families
64-KB CPU address space with banked memory management unit for greater than 64 KB
16-bit stack pointer (any size stack anywhere in 64-KB CPU address space)
16-bit index register (H:X) with powerful indexed addressing modes
8-bit accumulator (A)
Many instructions treat X as a second general-purpose 8-bit register
Seven addressing modes:
— Inherent — Operands in internal registers
— Relative — 8-bit signed offset to branch destination
— Immediate — Operand in next object code byte(s)
Unique Partial Power Down (PPD) or “Listen” Receive Mode
MC1323x Advance Information, Rev. 1.2
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