WM8523GEDT/R Wolfson Microelectronics, WM8523GEDT/R Datasheet - Page 18

• Manufacturer Part Number: WM8523GEDT/R
• Description: DAC, STEREO, 2VRMS, 2CH, 20TSSOP
• Manufacturer: Wolfson Microelectronics

Specifications of WM8523GEDT/R

• Resolution (bits): 24bit
• Sampling Rate: 192kSPS
• Input Channel Type: Serial
• Digital Ic Case Style: TSSOP
• No. Of Pins: 20
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Base: RoHS Compliant
• Data Interface: I2C, Serial, SPI
• Supply Voltage Range - Analogue: 2.97V To 3.63V
• Rohs Compliant: Yes

WM8523
w
I
In I
a bi-directional data pin. To allow arbitration of multiple slaves (and/or multiple masters) on the same
interface, the WM8523 transmits logic 1 by tri-stating the SDA pin, rather than pulling it high. An external
pull-up resistor is required to pull the SDA line high so that the logic 1 can be recognised by the master.
In order to allow many devices to share a single I
bit device address (this is not the same as the 8-bit address of each register in the WM8523). The
device address is determined by the logic level on the SDOUT and CS
LSB of the device address is the R/W ¯ ¯ bit; this bit is set to logic 1 for “Read” and logic 0 for “Write”.
Table 7 Control Interface Device Address Selection
The WM8523 operates as an I
with a high to low transition on SDA while SCLK remains high. This indicates that a device address,
register address and data will follow. All devices on the I
the next eight bits on SDA (7-bit device address + Read/Write bit, MSB first). If the device address
received matches the device address of the WM8523, then the WM8523 responds by pulling SDA low on
the next clock pulse (ACK). If the device address is not recognised or the R/W ¯ ¯ bit is ‘1’ when operating
in write only mode, the WM8523 returns to the idle condition and waits for a new start condition and valid
address.
If the device address matches the device address of the WM8523, the data transfer continues as
described below. The controller indicates the end of data transfer with a low to high transition on SDA
while SCLK remains high. After receiving a complete address and data sequence the WM8523 returns
to the idle state and waits for another start condition. If a start or stop condition is detected out of
sequence at any point during data transfer (i.e. SDA changes while SCLK is high), the device returns to
the idle condition.
The WM8523 supports the following read and write operations:
2
C CONTROL MODE
2
C mode, the WM8523 is a slave device on the control interface; SCLK is a clock input, while SDA is
•
•
SDOUT
Single write
Single read
ADDR1
0
0
1
1
2
C slave device only. The controller indicates the start of data transfer
ADDR0
CS
¯ ¯
0
1
0
1
2
C control bus, every device on the bus has a unique 7-
2
C bus respond to the start condition and shift in
DEVICE ADDRESS
0011 1100 (3Ch)
0011 1110 (3Eh)
0011 0100 (34h)
0011 0110 (36h)
¯ ¯ pins as shown in Table 7. The
PP, Rev 3.0, July 2009
Pre-Production
18