EPF10K30ETC144-1N Altera, EPF10K30ETC144-1N Datasheet - Page 61

• Manufacturer Part Number: EPF10K30ETC144-1N
• Description: IC PLD 1728 MACROCELL 100MHZ TQFP144
• Manufacturer: Altera
• Series: FLEX 10KEr

Specifications of EPF10K30ETC144-1N

• No. Of Macrocells: 1728
• No. Of I/o's: 102
• Global Clock Setup Time: 0.4ns
• Frequency: 100MHz
• Supply Voltage Range: 2.375V To 2.625V
• Operating Temperature Range: 0°C To +70°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Altera Corporation
Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10) This parameter is measured with the measurement and test conditions, including load, specified in the PCI Local
t
t
t
t
t
t
INSUBIDIR
INHBIDIR
INH
OUTCOBIDIR
XZBIDIR
ZXBIDIR
Table 30. External Bidirectional Timing Parameters
Symbol
Microparameters are timing delays contributed by individual architectural elements. These parameters cannot be
measured explicitly.
Operating conditions: VCCIO = 3.3 V ±10% for commercial or industrial use.
Operating conditions: VCCIO = 2.5 V ±5% for commercial or industrial use in EPF10K30E, EPF10K50S,
EPF10K100E, EPF10K130E, and EPF10K200S devices.
Operating conditions: VCCIO = 3.3 V.
Because the RAM in the EAB is self-timed, this parameter can be ignored when the WE signal is registered.
EAB macroparameters are internal parameters that can simplify predicting the behavior of an EAB at its boundary;
these parameters are calculated by summing selected microparameters.
These parameters are worst-case values for typical applications. Post-compilation timing simulation and timing
analysis are required to determine actual worst-case performance.
Contact Altera Applications for test circuit specifications and test conditions.
This timing parameter is sample-tested only.
Bus Specification, revision 2.2.
Setup time for bi-directional pins with global clock at same-row or same-
column LE register
Hold time for bidirectional pins with global clock at same-row or same-column
LE register
Hold time with global clock at IOE register
Clock-to-output delay for bidirectional pins with global clock at IOE register
Synchronous IOE output buffer disable delay
Synchronous IOE output buffer enable delay, slow slew rate= off
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Parameter
Note (9)
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
Conditions
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