M4A5-128/64-10YC LATTICE SEMICONDUCTOR, M4A5-128/64-10YC Datasheet
M4A5-128/64-10YC
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M4A5-128/64-10YC Summary of contents
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FEATURES High-performance, EE CMOS 3.3-V & 5-V CPLD families Flexible architecture for rapid logic designs TM — Excellent First-Time-Fit TM — SpeedLocking performance for guaranteed fixed timing — Central, input and output switch matrices for 100% routability and 100% pin-out ...
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M4-32/32 Feature M4LV-32/32 Macrocells 32 Maximum User I/O Pins 32 t (ns) 7 (MHz) 111 CNT t (ns) 5.5 COS t (ns) 5.5 SS Static Power (mA) 25 JTAG Compliant Yes PCI Compliant Yes Notes: 1. For information ...
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... TBD 55 Yes Yes Yes Yes Yes Yes M4A5-96 M4A5-128 M4A5-192 64 96 128 5.5 5.5 5.5 167 167 4.0 4.0 4.0 3.5 3.5 3.5 TBD 55 Yes Yes Yes Yes Yes Yes ...
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... The MACH 4 devices offer densities ranging from 32 to 512 macrocells with 100% utilization and 100% pin-out retention. Both the MACH 4 and the MACH 4A families offer 5-V (M4-xxx and M4A5-xxx) and 3.3-V (M4LV- xxx and M4A3-xxx) operation. ...
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... M4A5-64 2 M4A3- M4A5-96 3 M4A3-128 C 3 M4A5-128 2 M4A3-192 2 M4A5-192 2 M4A3-256 2 M4A5-256 2 M4A3-384 2 M4A3-512 Notes Commercial Industrial 2. Advance information is shaded. Please contact a Lattice/Vantis sales representative for details on availability. 3. Preliminary information. The MACH 4 family offers 20 density-I/O combinations in Thin Quad Flat Pack (TQFP), Plastic Quad Flat Pack (PQFP), Plastic Leaded Chip Carrier (PLCC), Ball Grid Array (BGA), fine-pitch BGA (fpBGA), and chip-array BGA (caBGA) packages ranging from 44 to 352 pins (Tables 5 and 6) ...
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... Advance information is shaded. Please contact a Lattice/Vantis sales representative for details on availability. 2. Preliminary information. 6 3.3 V Devices 1 M4A3-96 M4A3-128 M4A3-192 2 48+8 64+6 2 64+6 1 64+6 96+16 96+ Devices M4A5-96 M4A5-128 M4A5-192 48+8 64+6 64+6 96+16 MACH 4 Family M4A3-256 M4A3-384 M4A3-512 128+4 132 132 128+4 128+14, 160 160 160 192 192 128+14 192 ...
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FUNCTIONAL DESCRIPTION The fundamental architecture of MACH 4 devices (Figure 1) consists of multiple, optimized PAL blocks interconnected by a central switch matrix. The central switch matrix allows communication between PAL blocks and routes inputs to the PAL blocks. Together, ...
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... M4-96/48, M4LV-96/48 M4-128/64, M4LV-128/64 M4-128N/64, M4LV-128N/64 M4-192/96, M4LV-192/96 M4-256/128, M4LV-256/128 2:1 Yes Yes Yes Yes MACH 4A Devices M4A3-64/32, M4A5-64/32 M4A3-96/48, M4A5-96/48 M4A3-128/64, M4A5-128/64 M4A3-192/96, M4A5-192/96 M4A3-256/128, M4A5-256/128 M4A3-384 M4A3-512 2:1 Yes Yes Yes Yes MACH 4 Family M4-32/32 M4LV-32/32 1:1 Yes No Yes ...
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... M4-192/96 and M4LV-192/96 M4-256/128 and M4LV-256/128 M4A3-32/32 and M4A5-32/32 M4A3-64/32 and M4A5-64/32 M4A3-96/48 and M4A5-96/48 M4A3-128/64 and M4A5-128/64 M4A3-192/96 and M4A5-192/96 M4A3-256/128 and M4A5-256/128 M4A3-256/160 and M4A3-256/192 M4A3-384 M4A3-512 Logic Allocator Within the logic allocator, product terms are allocated to macrocells in “product term clusters.” ...
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The configuration is always set by the mode of the macrocell that the cluster will drive if not routed away, regardless of the actual routing. In addition, there is an extra product term ...
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Table 10. Logic Allocator for All MACH 4 and MACH 4A Devices (except M4(LV)-32/32 and M4A(3,5)-32/32) Output Macrocell Table 11. Logic Allocator for M4(LV)-32/32 ...
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Basic cluster with XOR 0 d. Basic cluster routed away; single-product-term, active high Figure 3. Logic Allocator Configurations: Synchronous Mode a. Basic cluster with XOR 0 d. Basic cluster routed away; single-product-term, active high Figure 4. Logic Allocator Configurations: ...
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Macrocell The macrocell consists of a storage element, routing resources, a clock multiplexer, and initialization control. The macrocell has two fundamental modes: synchronous and asynchronous (Figure 5). The mode chosen only affects clocking and initialization in the macrocell. Power-Up Reset ...
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The flip-flop can be configured as a D-type or T-type latch. J-K or S-R registers can be synthesized. The primary flip-flop configurations are shown in Figure 6, although others are possible. Flip-flop functionality is defined in Table 12. Note that ...
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Configuration D-type Register T-type Register D-type Latch Note: 1. Polarity of CLK/LE can be programmed Although the macrocell shows only one input to the register, the XOR gate in the logic allocator allows the D-, T-type register to emulate J-K, ...
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A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, providing flexibility. In asynchronous mode (Figure 8), a single individual product term is provided for initialization. It can be selected to control reset or preset. ...
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M10 M11 M12 M13 M14 M15 Each I/O cell can Each macrocell can drive choose one of 8 one of 4 I/O cells in MACH 4 macrocells in and MACH ...
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Table 14. Output Switch Matrix Combinations for MACH 4 and MACH 4A Macrocell I/O6 I/O7 Table 15. Output Switch Matrix Combinations for MACH 4 and MACH 4A Devices with 1:1 Macrocell-I/O Cell Ratio except M4(LV)-32/32 and M4A(3,5)-32/32 Macrocell M0 M1 ...
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Table 16. Output Switch Matrix Combinations for M4(LV)-32/32 and M4A(3,5)-32/32 Macrocell M0, M1, M2, M3, M4, M5, M6, M7 M8, M9, M10, M11, M12, M13, M14, M15 I/O Cell I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7 I/O8, I/O9, I/O10, ...
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I/O Cell The I/O cell (Figures 10 and 11) simply consists of a programmable output enable, a feedback path, and flip-flop (except MACH 4 and MACH 4A devices with 1:1 macrocell-I/O cell ratio.) An individual output enable product term is ...
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Figure 12. MACH 4 and MACH 4A with 2:1 Macrocell-I/O Cell Ratio - Input Switch Matrix PAL Block Clock Generation Each MACH 4 device has four clock pins that can also be used as inputs. These pins drive a clock ...
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Table 17. PAL Block Clock Combinations Block CLK0 GCLK0 GCLK1 GCLK0 GCLK1 Note: 1. Values in parentheses are for the M4(LV)-32/32, M4A(3,5)-32/32, M4(LV)-64/32 and M4A(3,5)-64/32. This feature provides high flexibility for partitioning state machines and dual-phase ...
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MACH 4 TIMING MODEL The primary focus of the MACH 4 timing model is to accurately represent the timing in a MACH 4 device, and at the same time, be easy to understand. This model accurately describes all combinatorial and ...
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IEEE 1149.1-COMPLIANT BOUNDARY SCAN TESTABILITY All MACH 4 devices, except the M4(LV)-128N/64, have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows functional testing of the circuit board on which the device is mounted through a ...
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All MACH 4A devices have a programmable bit that configures all inputs and I/Os with either pull-up or Bus-Friendly characteristics. If the device is configured in pull-up mode, all inputs and I/O pins are weakly pulled up. For the circuit ...
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INPUT SWITCH MATRIX Figure 16. PAL Block for MACH 4 and MACH 4A with 2:1 Macrocell - I/O Cell Ratio 26 M4(LV)-64/32, M4A(3, 5)-64/32 M4(LV)-96/48, M4A(3, 5)-96/48 M4(LV)-128/64, M4A(3, 5)-128/64 CLOCK A 16 GENERATOR B ...
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INPUT 32 SWITCH MATRIX Figure 17. PAL Block for MACH 4A Devices with 1:1 Macrocell-I/O Cell Ratio (except M4A (3,5)-32/32) CLOCK GENERATOR MACROCELL MACROCELL MACROCELL ...
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INPUT 32 SWITCH MATRIX Figure 18. PAL Block for M4(LV)-32/32 and M4A (3,5)-32/32 28 CLK0/I0 CLK0/I1 CLOCK GENERATOR MACROCELL MACROCELL MACROCELL ...
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BLOCK DIAGRAM – M4(LV)-32/32 AND M4A(3,5)-32/ Block A I/O8–I/O15 8 I/O Cells 8 Output Switch 8 Matrix Macrocells AND Logic Array and Logic Allocator 16 33 Central Switch ...
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BLOCK DIAGRAM – M4(LV)-64/32 AND M4A(3,5)-64/ Block A I/O0–I/O7 8 I/O Cells 8 4 Output Switch Matrix Macrocells AND Logic ...
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BLOCK DIAGRAM – M4(LV)-96/48 AND M4A(3,5)-96/48 Clock Generator Clock Generator Clock Generator I2, I3, I6, I7 Input Switch Input Switch Matrix Matrix OE Input Switch Input Switch Matrix Matrix OE Input Switch Input Switch Matrix Matrix OE CLK0/I0, CLK1/I1, CLK2/I4, ...
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BLOCK DIAGRAM – M4(LV)-128N/64, M4(LV)-128/64 AND M4A(3,5)-128/64 Clock Generator Clock Generator Clock Generator Clock Generator 32 I2, I5 Input Switch Input Switch Matrix Matrix OE OE Input Switch Input Switch Matrix Matrix OE OE Input Switch Input Switch Matrix Matrix ...
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BLOCK DIAGRAM – M4(LV)-192/96 AND M4A(3,5)-192/96 Block B I/O8–I/O15 8 I/O Cells 8 4 Output Switch Matrix Macrocells AND Logic Array and Logic Allocator 24 34 Block C I/O16–I/O23 Block ...
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BLOCK DIAGRAM – M4(LV)-256/128 AND M4A(3,5)-256/128 Block B I/O8–I/O15 8 I/O Cells 8 4 Output Switch Matrix Macrocells AND Logic Array and Logic Allocator ...
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BLOCK DIAGRAM – M4A3-384/192 Block B I/O8–I/O15 8 Detail A I/O Cells 8 4 Output Switch Matrix Macrocells AND Logic Array and Logic Allocator ...
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BLOCK DIAGRAM - M4A3-512/256 Block B I/O8–I/O15 8 Detail A I/O Cells 8 4 Output Switch Matrix Macrocells AND Logic Array and Logic Allocator ...
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... ABSOLUTE MAXIMUM RATINGS M4 and M4A5 Storage Temperature . . . . . . . . . . . . . .- +150 C Ambient Temperature with Power Applied . . . . . . . . . . . . . . - +100 C Device Junction Temperature . . . . . . . . . . . . . +130 C Supply Voltage with Respect to Ground . . . . . . . . . . . -0 +7 Input Voltage . . . . . . . . . . . . -0 Static Discharge Voltage . . . . . . . . . . . . . . . . . 2000 V Latchup Current ( +85 C 200 mA A Str esses above those listed under Absolute Maximum Ratings may cause permanent device failure ...
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ABSOLUTE MAXIMUM RATINGS M4LV and M4A3 Storage Temperature . . . . . . . . . . . . . .- +150 C Ambient Temperature with Power Applied . . . . . . . . . ...
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MACH 4 TIMING PARAMETERS OVER OPERATING RANGES Combinatorial Delay: t Internal combinatorial propagation delay PDi t Combinatorial propagation delay PD Registered Delays: t Synchronous clock setup time, D-type register SS t Synchronous clock setup time, T-type register SST t Asynchronous ...
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MACH 4 TIMING PARAMETERS OVER OPERATING RANGES Input Latch Delays with ZHT Option: t Input latch setup time - ZHT SILZ t Input latch hold time - ZHT HILZ t Transparent input latch to internal feedback - ZHT PDILZi Output ...
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MACH 4 TIMING PARAMETERS OVER OPERATING RANGES Frequency: External feedback, D-type, Min of 1/(t WLS 1/( COS External feedback, T-type, Min of 1/(t WLS 1/( SST COS Internal feedback (f ), D-type, CNT ...
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MACH 4A TIMING PARAMETERS OVER OPERATING RANGES t Asynchronous clock to internal output COAi t Asynchronous clock to output COA Latched Delays: t Synchronous latch setup time SSL t Asynchronous latch setup time SAL t Synchronous latch hold time HSL ...
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MACH 4A TIMING PARAMETERS OVER OPERATING RANGES Input Register Delays with ZHT Option: t Input register setup time - ZHT SIRZ t Input register hold time - ZHT HIRZ Input Latch Delays with ZHT Option: t Input latch setup time ...
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MACH 4A TIMING PARAMETERS OVER OPERATING RANGES Frequency: External feedback, D-type, Min of 1/(t WLS 1/( WHS SS COS External feedback, T-type, Min of 1/(t WLS 1/( WHS ...
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CAPACITANCE Parameter Symbol Parameter Description C Input capacitance IN C Output capacitance I/O Note: 1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where this parameter may ...
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HP: High Power LP: Low Power 250 200 150 Icc (mA) 100 Figure 21. MACH 4A Device Dynamic Icc Curves at High and Low Power ...
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PLCC CONNECTION DIAGRAM (M4(LV)-32/32, M4A(3,5)-32/32, M4(LV)-64/32 AND M4A(3,5)-64/32) Top View M4(LV)-64/32 M4A(3,5)-64 I/O7 TDI CLK0/I0 M4(LV)-32/32 GND M4A(3,5)-32/32 TCK I/O9 A10 B2 I/O10 A11 B3 I/O11 ...
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TQFP CONNECTION DIAGRAM (M4(LV)-32/32, M4A(3,5)-32/32, M4(LV)-64/32 AND M4A(3,5)-64/32) Top View M4(LV)-64/32 M4A(3,5)-64 I/O7 TDI M4(LV)-32/32 CLK0/I0 M4A(3,5)-32/32 GND TCK I/O9 A10 B2 I/O10 A11 B3 I/O11 ...
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TQFP CONNECTION DIAGRAM (M4(LV)-32/32, M4A(3,5)-32/32, M4(LV)-64/32 AND M4A(3,5)-64/32) Top View M4(LV)-64/32 M4A(3,5)-64 I/O7 TDI CLK0/I0 M4(LV)-32/32 NC M4A(3,5)-32/32 GND TCK I/O9 A10 B2 I/O10 A11 B3 ...
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TQFP CONNECTION DIAGRAM (M4(LV)-96/48 AND M4A(3,5)-96/48) Top View NC 1 TDI I/O10 9 B3 I/O11 10 I0/CLK0 ...
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PLCC CONNECTION DIAGRAM (M4(LV)-128N/64) Top View I/ I/O9 B5 I/O10 14 B4 I/O11 I/O12 B2 17 I/O13 B1 18 I/O14 B0 I/O15 19 CLK ...
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PQFP CONNECTION DIAGRAM (M4(LV)-128/64 AND M4A(3,5)-128/64) Top View GND GND TDI I5 B7 I/O8 B6 I/O9 B5 I/O10 B4 I/O11 B3 I/O12 B2 I/O13 B1 I/O14 B0 I/O15 IO/CLK0 GND GND I1/CLK1 C0 I/O16 C1 ...
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TQFP CONNECTION DIAGRAM (M4(LV)-128/64 AND M4A(3,5)-128/64) Top View GND 1 TDI I/O10 5 B4 I/O11 6 B3 I/O12 7 B2 I/O13 8 B1 I/O14 9 B0 I/O15 10 I0/CLK0 11 V ...
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TQFP CONNECTION DIAGRAM (M4(LV)-192/96 AND M4A(3,5)-192/96) Top View GND 1 TDI ...
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TQFP CONNECTION DIAGRAM - M4A3-256/128, M4A3-192/128, M4A3-128/128, AND M4A3-384/132 Top View GND 1 GND TDI TDI 2 C7 I/O16 C7 I/O16 3 C6 I/O17 C6 I/O17 4 C5 I/O18 C5 I/O18 5 C4 I/O19 C4 I/O19 6 C3 I/O20 ...
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PQFP CONNECTION DIAGRAM - M4A3-256/128, M4-256/128, M4LV-256/128, AND M4A3-384/160 Top View GND GND 1 TDI TDI 2 C7 I/O18 C7 I/O16 3 C6 I/O19 C6 I/O17 4 C5 I/O20 C5 I/O18 5 C4 I/O21 C4 I/O19 6 C3 I/O22 ...
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BGA CONNECTION DIAGRAM (M4(LV)-256/128 AND M4A(3,5)-256/128) Bottom View I/O108 I/O105 A GND N/C GND GND N4 N1 I/O113 I/O109 I/O106 I/O103 B GND N I/O116 I/O111 I/O107 C N/C ...
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BGA CONNECTION DIAGRAM - M4A3-384/192 Bottom View I/O11 I/O44 I/O58 A GND GND GND FX7 FX6 CX6 I/O12 I/O28 I/O45 I/O59 I/O64 B GND GX7 FX5 FX3 CX7 CX5 I/O0 I/O13 I/O46 I/O60 ...
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MACH 4 PRODUCT ORDERING INFORMATION MACH 4 Devices Commercial & Industrial - 3.3V and 5V Lattice/Vantis programmable logic products are available with several ordering options. The order number (Valid Com- bination) is formed by a combination of: FAMILY TYPE M4- ...
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... Lattice/Vantis programmable logic products are available with several ordering options. The order number (Valid Com- bination) is formed by a combination of: FAMILY TYPE M4A3- = MACH 4 Family Low Voltage Advanced Feature (3.3 M4A5- = MACH 4 Family Advanced Feature (5-V V MACROCELL DENSITY Macrocells 192 = 192 Macrocells Macrocells 256 = 256 Macrocells Macrocells ...
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... MACHPRO, MACHXL, and PAL are registered trademarks of Lattice Semiconductor Corporation. Other product names used in this publication are for indentification purposes only and may be trademarks of their respective companies. 5V Industrial Combinations JC, VC, VC48 M4A5-32/32 JC, VC, VC48 M4A5-64/32 VC M4A5-96/48 YC, VC M4A5-128/64 VC M4A5-192/96 YC, AC M4A5-256/128 Valid Combinations ...