74HCT107N NXP Semiconductors, 74HCT107N Datasheet - Page 2

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74HCT107N

Manufacturer Part Number
74HCT107N
Description
IC, 74HCT CMOS, 74HCT107, DIP14, 5V
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74HCT107N

Flip-flop Type
JK
Propagation Delay
19ns
Frequency
73MHz
Output Current
4mA
Supply Voltage Range
4.5V To 5.5V
Logic Case Style
DIP
No. Of Pins
14
Operating
RoHS Compliant
Trigger Type
Negative Edge
Ic Output Type
Complementary
Rohs Compliant
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74HCT107N
Manufacturer:
PHILIPS
Quantity:
1 032
Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT107 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
ORDERING INFORMATION
See
December 1990
t
f
C
C
PHL
max
Output capability: standard
I
Dual JK flip-flop with reset; negative-edge trigger
I
PD
CC
f
f
C
V
For HCT the condition is V
i
o
“74HC/HCT/HCU/HCMOS Logic Package Information”
/ t
SYMBOL
CC
PD
= input frequency in MHz
L
category: flip-flops
= output frequency in MHz
(C
PLH
= output load capacitance in pF
P
= supply voltage in V
is used to determine the dynamic power dissipation (P
L
D
= C
V
amb
CC
PD
2
= 25 C; t
V
f
o
propagation delay
maximum clock frequency
input capacitance
power dissipation
CC
) = sum of outputs
capacitance per flip-flop
nCP to nQ
nCP to nQ
nR to nQ, nQ
2
f
r
i
= t
PARAMETER
I
I
f
= GND to V
= GND to V
= 6 ns
(C
L
V
CC
2
CC
CC
f
o
) where:
1.5 V.
C
V
notes 1 and 2
CC
L
= 15 pF;
= 5 V
2
.
CONDITIONS
The 74HC/HCT107 are dual negative-edge triggered
JK-type flip-flops featuring individual J, K, clock (nCP) and
reset (nR) inputs; also complementary Q and Q outputs.
The J and K inputs must be stable one set-up time prior to
the HIGH-to-LOW clock transition for predictable
operation.
The reset (nR) is an asynchronous active LOW input.
When LOW, it overrides the clock and data inputs, forcing
the Q output LOW and the Q output HIGH.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
D
in W):
16
16
16
78
3.5
30
HC
TYPICAL
74HC/HCT107
Product specification
16
18
17
73
3.5
30
HCT
ns
ns
ns
MHz
pF
pF
UNIT

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