25LC1024-I/SN Microchip Technology, 25LC1024-I/SN Datasheet - Page 12

• Manufacturer Part Number: 25LC1024-I/SN
• Description: IC, EEPROM, 1MBIT, SERIAL, 20MHZ, SOIC-8
• Manufacturer: Microchip Technology

Specifications of 25LC1024-I/SN

• Memory Size: 1Mbit
• Ic Interface Type: SPI
• Clock Frequency: 20MHz
• Supply Voltage Range: 2.5V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Memory Configuration: 128K X 8
• Interface Type: Serial, SPI

25LC1024
2.5
The Write Status Register instruction (WRSR) allows the
user to write to the nonvolatile bits in the STATUS
register as shown in Table 2-2. The user is able to
select one of four levels of protection for the array by
writing to the appropriate bits in the STATUS register.
The array is divided up into four segments. The user
has the ability to write-protect none, one, two, or all four
of the segments of the array. The partitioning is
controlled as shown in Table 2-3.
TABLE 2-3:
FIGURE 2-7:
DS22064C-page 12
SCK
CS
SO
SI
BP1
Write Status Register Instruction
(WRSR)
0
0
1
1
0
0
ARRAY PROTECTION
0
WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
1
BP0
0
0
1
0
1
Instruction
2
0
3
0
4
Upper 1/2 (Sectors 2 & 3)
All (Sectors 0, 1, 2 & 3)
Upper 1/4 (Sector 3)
0
Array Addresses
(18000h-1FFFFh)
(10000h-1FFFFh)
(00000h-1FFFFh)
Write-Protected
5
High-Impedance
0
none
6
1
7
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bit for the WP pin. The
Write-Protect (WP) pin and the Write-Protect Enable
(WPEN) bit in the STATUS register control the
programmable hardware write-protect feature. Hard-
ware write protection is enabled when WP pin is low
and the WPEN bit is high. Hardware write protection is
disabled when either the WP pin is high or the WPEN
bit is low. When the chip is hardware write-protected,
only writes to nonvolatile bits in the STATUS register
are disabled. See Table 2-4 for a matrix of functionality
on the WPEN bit.
See Figure 2-7 for the WRSR timing sequence.
7
8
6
9
Data to STATUS register
10
5
Lower 3/4 (Sectors 0, 1 & 2)
11
4
Lower 1/2 (Sectors 0 & 1)
All (Sectors 0, 1, 2 & 3)
Array Addresses
(00000h-1FFFFh)
(00000h-0FFFFh)
(00000h-17FFFh)
© 2008 Microchip Technology Inc.
12
3
Unprotected
none
13
2
14
1
15
0