SST25VF080B-80-4I-QAE SILICON STORAGE TECHNOLOGY, SST25VF080B-80-4I-QAE Datasheet - Page 18

• Manufacturer Part Number: SST25VF080B-80-4I-QAE
• Description: MEMORY, FLASH, 8MBIT, SPI, 8WSON
• Manufacturer: SILICON STORAGE TECHNOLOGY

Specifications of SST25VF080B-80-4I-QAE

• Memory Size: 8Mbit
• Clock Frequency: 80MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: WSON
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (18-Jun-2010)
• Memory Type: Flash
• Memory Configuration: 1M X 8
• Interface Type: Serial, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A Microchip Technology Company
©2011 Silicon Storage Technology, Inc.
Chip-Erase
Read-Status-Register (RDSR)
The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored
if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction
must be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence.
The Chip-Erase instruction is initiated by executing an 8-bit command, 60H or C7H. CE# must be driven
high before the instruction is executed. The user may poll the Busy bit in the software status register or wait
T
sequence.
Figure 15:Chip-Erase Sequence
The Read-Status-Register (RDSR) instruction allows reading of the status register. The status register
may be read at any time even during a Write (Program/Erase) operation. When a Write operation is in
progress, the Busy bit may be checked before sending any new commands to assure that the new
commands are properly received by the device. CE# must be driven low before the RDSR instruction is
entered and remain low until the status data is read. Read-Status-Register is continuous with ongoing
clock cycles until it is terminated by a low to high transition of the CE#. See Figure 16 for the RDSR
instruction sequence.
Figure 16:Read-Status-Register (RDSR) Sequence
CE
SCK
CE#
for the completion of the internal self-timed Chip-Erase cycle. See Figure 15 for the Chip-Erase
SO
SI
MODE 3
MODE 0
MSB
0
1
HIGH IMPEDANCE
2
SCK
CE#
SO
3
SI
05
MODE 3
MODE 0
4
18
5
HIGH IMPEDANCE
MSB
0 1 2 3 4 5 6 7
6
60 or C7
7
MSB
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
8
1296 ChEr.0
9
8 Mbit SPI Serial Flash
10
Register Out
11
Status
12
13
SST25VF080B
1296 RDSRseq.0
14
S71296-05-000
Data Sheet
02/11