AM29F016D-90EF Spansion Inc., AM29F016D-90EF Datasheet - Page 14

• Manufacturer Part Number: AM29F016D-90EF
• Description: IC, FLASH, 16MBIT, 90NS, TSOP-48
• Manufacturer: Spansion Inc.

Specifications of AM29F016D-90EF

• Memory Type: Flash
• Memory Size: 16Mbit
• Memory Configuration: 2M X 8
• Ic Interface Type: Parallel
• Access Time: 90ns
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: TSOP
• No. Of Pins: 48
• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Bottom/Top
• Address Bus: 21b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 4.5 to 5.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 2M
• Supply Current: 40mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

addresses. Once V
pin, all the previously protected sector groups are
protected again. Figure
the Temporary Sector Group Unprotect diagram (Fig-
ure 16) shows the timing waveforms, for this feature.
12
Notes:
1. All protected sector groups unprotected.
2. All previously protected sector groups are protected
Figure 1. Temporary Sector Group Unprotect
once again.
ID
Sector Group Unprotect
Operation
Program Operations
Completed (Note 2)
is removed from the RESET#
Perform Erase or
RESET# = VID
RESET# = VIH
1
Temporary
(Note 1)
shows the algorithm, and
START
D A T A
Am29F016D
S H E E T
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by
spurious system level signals during V
power-down transitions, or from system noise.
Low V
When V
cept any write cycles. This protects data during V
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V
proper signals to the control pins to prevent uninten-
tional writes when V
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE#
= V
cle, CE# and WE# must be a logical zero while OE#
is a logical one.
Power-Up Write Inhibit
If WE# = CE# = V
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
IL
, CE# = V
CC
CC
Write Inhibit
is less than V
IH
IL
or WE# = V
LKO
and OE# = V
CC
. The system must provide the
is greater than V
LKO
, the device does not ac-
21444E9 November 16, 2009
IH
. To initiate a write cy-
IH
during power up, the
CC
LKO
power-up and
.
CC
CC