AM29F032B-75EF Spansion Inc., AM29F032B-75EF Datasheet - Page 20

IC, FLASH, 32MBIT, 75NS, TSOP-40

AM29F032B-75EF

Manufacturer Part Number
AM29F032B-75EF
Description
IC, FLASH, 32MBIT, 75NS, TSOP-40
Manufacturer
Spansion Inc.
Datasheets

Specifications of AM29F032B-75EF

Memory Type
Flash
Memory Size
32Mbit
Memory Configuration
4M X 8
Access Time
75ns
Supply Voltage Range
4.75V To 5.25V
Memory Case Style
TSOP
No. Of Pins
40
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AM29F032B-75EF
Manufacturer:
TI
Quantity:
12 000
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#.
sections describe the functions of these bits. DQ7,
RY/BY#, and DQ6 each offer a method for determining
whether a program or erase operation is complete or in
progress. These three bits are discussed first.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Algor ithm is in
progress or completed, or whether the device is in
Erase Suspend. Data# Polling is valid after the rising
edge of the final WE# pulse in the program or erase
command sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to pro-
g r a m m i n g d u r i n g E r a s e S u s p e n d . W h e n t h e
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap-
proximately 2 µs, then the device returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase al-
gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in-
formation on DQ7.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the de-
vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7–
DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. The Data# Poll-
ing Timings (During Embedded Algorithms) figure in
the “AC Characteristics” section illustrates this.
18
Table 6 on page 21
and the following sub-
D A T A
Am29F032B
S H E E T
Table 6 on page 21
on DQ7.
Notes:
1. VA = Valid address for programming. During a sector
2. DQ7 should be rechecked even if DQ5 = “1” because
No
erase operation, a valid address is an address within
any sector selected for erasure. During chip erase, a
valid address is any non-protected sector address.
DQ7 may change simultaneously with DQ5.
Figure 4. Data# Polling Algorithm
Figure 4
Read DQ7–DQ0
Read DQ7–DQ0
DQ7 = Data?
DQ7 = Data?
Addr = VA
Addr = VA
DQ5 = 1?
START
FAIL
shows the Data# Polling algorithm.
shows the outputs for Data# Polling
No
Yes
No
21610D5 November 2, 2006
Yes
Yes
PASS

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