AM29F400BT-55EF Spansion Inc., AM29F400BT-55EF Datasheet - Page 11

• Manufacturer Part Number: AM29F400BT-55EF
• Description: IC, FLASH, 4MBIT, 55NS, TSOP-48
• Manufacturer: Spansion Inc.

Specifications of AM29F400BT-55EF

• Memory Type: Flash
• Memory Size: 4Mbit
• Memory Configuration: 512K X 8 / 256K X 16
• Access Time: 55ns
• Supply Voltage Range: 4.75V To 5.25V
• Memory Case Style: TSOP
• No. Of Pins: 48
• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 55ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 19/18Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 4.75 to 5.25V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 512K/256K
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Compliant

After the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings apply
in this mode. Refer to the “Autoselect Mode” and
“Autoselect Command Sequence” sections for more
information.
I
active current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
read specifications apply. Refer to “The Erase Resume
command is valid only during the Erase Suspend
mode.” for more information, and to “AC Characteris-
tics” for timing diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V
(Note that this is a more restricted voltage range than
V
CE# and RESET# pins are both held at V
requires standard access time (t
when the device is in either of these standby modes,
before it is ready to read data.
The device also enters the standby mode when the
RESET# pin is driven low. Refer to the next section,
“RESET#: Hardware Reset Pin”.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
November 11, 2009 21505E8
CC2
IH
.) The device enters the TTL standby mode when
in the DC Characteristics table represents the
CE
) for read access
IH
. The device
CC
D A T A
± 0.5 V.
Am29F400B
CC
S H E E T
In the CMOS and TTL/NMOS-compatible DC Charac-
teristics tables, I
specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the
RESET# pin is driven low for at least a period of t
device immediately terminates any operation in
progress, tristates all output pins, and ignores all read/
write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to
reading array data. The operation that was interrupted
should be reinitiated once the device is ready to accept
another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
the TTL standby mode; if RESET# is held at V
V, the device enters the CMOS standby mode.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase oper-
ation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t
rithms). The system can read data t
RESET# pin returns to V
Refer to the AC Characteristics tables for RESET#
parameters and to Figure 10 for the timing diagram.
Output Disable Mode
When the OE# input is at V
disabled. The output pins are placed in the high imped-
ance state.
READY
(during Embedded Algorithms). The
CC3
READY
represents the standby current
(not during Embedded Algo-
IH
.
IH
, output from the device is
IL
, the device enters
RH
after the
SS
RP,
±0.5
the
9