S29GL01GP13FFIV10 Spansion Inc., S29GL01GP13FFIV10 Datasheet - Page 32

• Manufacturer Part Number: S29GL01GP13FFIV10
• Description: IC, FLASH, 1000MBIT, 130NS, TSOP-64
• Manufacturer: Spansion Inc.

Specifications of S29GL01GP13FFIV10

• Memory Type: Flash
• Memory Size: 1000Mbit
• Memory Configuration: 128K X 16
• Ic Interface Type: Parallel
• Access Time: 130ns
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 64
• Cell Type: NOR
• Density: 1Gb
• Access Time (max): 130ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 27/26Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: Fortified BGA
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 128M/64M
• Supply Current: 110mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

32
7.7.4
Chip Erase Command Sequence
Chip erase is a six-bus cycle operation as indicated by
Embedded Erase algorithm, which does not require the system to preprogram prior to erase. The Embedded
Erase algorithm automatically preprograms and verifies the entire memory to an all zero data pattern prior to
electrical erase. After a successful chip erase, all locations of the chip contain FFFFh. The system is not
required to provide any controls or timings during these operations. The
shows the address and data requirements for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that sector returns to the read mode and addresses are no
longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. Refer
to “Write Operation Status” for information on these status bits.
The Unlock Bypass feature allows the host system to send program commands to the Flash device without
first writing unlock cycles within the command sequence. See
function.
Any commands written during the chip erase operation are ignored. However, note that a hardware reset
immediately terminates the erase operation. If that occurs, the chip erase command sequence should be
reinitiated once that sector has returned to reading array data, to ensure the entire array is properly erased.
Software Functions and Sample Code
The following is a C source code example of using the chip erase function. Refer to the Spansion Low Level
Driver User’s Guide (available on www.spansion.com) for general information on Spansion Flash memory
software development guidelines.
Cycle
/* Example: Chip Erase Command */
/* Note: Cannot be suspended
1
2
3
4
5
6
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0080;
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0010;
Chip Erase Command
Setup Command
Description
Unlock
Unlock
Unlock
Unlock
S29GL-P MirrorBit
*/
(LLD Function = lld_ChipEraseCmd)
Operation
Table 7.9 Chip Erase
D a t a
Write
Write
Write
Write
Write
Write
®
Flash Family
/* write unlock cycle 1
/* write unlock cycle 2
/* write setup command
/* write additional unlock cycle 1 */
/* write additional unlock cycle 2 */
/* write chip erase command
S h e e t
Table 12.1 on page
Byte Address
Base + AAAh
Base + AAAh
Base + AAAh
Base + AAAh
Base + 555h
Base + 555h
Section 7.7.8
Command Definitions on page 68
S29GL-P_00_A13 November 17, 2010
Word Address
69. These commands invoke the
Base + 2AAh
Base + 2AAh
Base + 555h
Base + 555h
Base + 555h
Base + 555h
for details on the Unlock Bypass
*/
*/
*/
*/
00AAh
00AAh
0055h
0080h
0055h
0010h
Data