PIC12F1822-I/MF Microchip Technology, PIC12F1822-I/MF Datasheet
PIC12F1822-I/MF
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PIC12F1822-I/MF Summary of contents
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... PIC12F/LF1822/PIC16F/LF1823 2010 Microchip Technology Inc. 8/14-Pin Flash Microcontrollers with nanoWatt XLP Technology Preliminary Data Sheet DS41413A ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Reference Clock Module: - Programmable clock output frequency and duty-cycle Special Microcontroller Features: • Full 5.5V operation – PIC12F1822/16F1823 • 1.8V-3.6V operation – PIC12LF1822/16LF1823 • Self-reprogrammable under software control • Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • ...
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... Data Signal Modulator module - Selectable modulator and carrier sources • SR Latch: - Multiple Set/Reset input options - Emulates 555 Timer applications PIC12F/LF1822/16F/LF1823 Family Types Program Data Memory Memory PIC12LF1822 2K 128 PIC12F1822 2K 128 PIC16LF1823 2K 128 PIC16F1823 2K 128 Note 1: One pin is input only. DS41413A-page 4 256 ...
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FIGURE 1: 8-PIN DIAGRAM FOR PIC12F/LF1822 PDIP, SOIC, DFN (1) (1) (1) (1) RX /DT /CCP1 /P1A /SRNQ/T1CKI/T1OSI/OSC1/CLKIN/RA5 (1) (1) (1) (1) (1) MDCIN2/T1G /P1B /TX /CK /SDO /CLKR/C1IN1-/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4 Note 1: Pin function is selectable via the APFCON register. TABLE ...
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FIGURE 2: 14-PIN DIAGRAM FOR PIC16F/LF1823 PDIP, SOIC, TSSOP T1CKI/T1OSI/OSC1/CLKIN/RA5 (1) (1) T1G /SDO /CLKR/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4 MCLR/V (1) MDCIN2/RX /DT (1) (1) MDOUT/TX /CK /P1B/SRNQ/C2OUT/RC4 (1) MDMIN/SS /P1C/C12IN3-/CPS7/AN7/RC3 Note 1: Pin function is selectable via the APFCON register ...
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FIGURE 3: 14-PIN DIAGRAM FOR PIC16F/LF1823 QFN T1CKI/T1OSI/OSC1/CLKIN/RA5 (1) (1) T1G /SDO /CLKR/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4 (1) MCLR/V /T1G /SS PP (1) (1) MDCIN2/RX /DT /CCP1/P1A/RC5 Note 1: Pin function is selectable via the APFCON register PIC16F/LF1823 (1) /RA3 ...
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... OSC1 CLKIN SCL — — Y — SCK SDA — — Y — SDI (1) SDO — MDCIN1 Y — (1) SS — MDMIN Y — — — MDOUT Y — — — MDCIN2 Y — — — — — — — — — 2010 Microchip Technology Inc. ...
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... Packaging Information.............................................................................................................................................................. 371 Appendix A: Revision History............................................................................................................................................................. 387 Appendix B: Device Differences ........................................................................................................................................................ 387 Index .................................................................................................................................................................................................. 389 The Microchip Web Site ..................................................................................................................................................................... 395 Customer Change Notification Service .............................................................................................................................................. 395 Customer Support .............................................................................................................................................................................. 395 Reader Response .............................................................................................................................................................................. 396 Product Identification System ............................................................................................................................................................ 397 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 ) ................................................................................................................................ 315 ™ Preliminary DS41413A-page 9 ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. DS41413A-page 10 Preliminary 2010 Microchip Technology Inc. ...
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... Digital Signal Modulator (DSM) EUSART Fixed Voltage Reference (FVR) SR Latch Capture/Compare/PWM Modules ECCP1 Comparators C1 C2 Master Synchronous Serial Ports MSSP Timers Timer0 Timer1 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 of the ● ● ● ● ● ● ● ● ● ● ● ...
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... See applicable chapters for more information on peripherals. 2: See Table 1-1 for peripherals available on specific devices. 3: PIC16F/LF1823 only. DS41413A-page 12 Program Flash Memory RAM CPU (Figure 2-1) ADC Timer1 DAC Comparators 10-Bit Modulator FVR EUSART CapSense Preliminary EEPROM PORTA (3) PORTC 2010 Microchip Technology Inc. ...
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... Legend Analog input or output CMOS = CMOS compatible input or output TTL = TTL compatible input High Voltage XTAL = Crystal Note 1: Pin functions can be assigned to one of two pin locations via software. See APFCON register (Register 12-1). 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Input Output Type Type TTL CMOS General purpose I/O ...
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... CMOS Capture/Compare/PWM 1. ST CMOS USART synchronous data. ST — USART asynchronous input. Power — Positive supply. Power — Ground reference. = Schmitt Trigger input with CMOS levels I Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels 2010 Microchip Technology Inc. ...
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... Legend Analog input or output CMOS = CMOS compatible input or output TTL = TTL compatible input High Voltage XTAL = Crystal Note 1: Pin functions can be assigned to one of two pin locations via software. See APFCON register (Register 12-1). 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Input Output Type Type TTL CMOS General purpose I/O ...
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... CMOS PWM output. ST CMOS Capture/Compare/PWM 1. ST CMOS USART synchronous data. ST — USART asynchronous input. ST — Modulator Carrier Input 2. = Schmitt Trigger input with CMOS levels I Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels 2010 Microchip Technology Inc. ...
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... Legend Analog input or output CMOS = CMOS compatible input or output TTL = TTL compatible input High Voltage XTAL = Crystal Note 1: Pin functions can be assigned to one of two pin locations via software. See APFCON register (Register 12-1). 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Input Output Type Type Power — ...
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... PIC12F/LF1822/16F/LF1823 NOTES: DS41413A-page 18 Preliminary 2010 Microchip Technology Inc. ...
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... Section 3.5 “Indirect Addressing” for more details. 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 28.0 “Instruction Set Summary” for more details. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Preliminary DS41413A-page 19 ...
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... Power-up Timer Oscillator Start-up Timer ALU ALU ALU Power- Reset Watchdog W Reg Timer Brown-out Reset Preliminary RAM Addr 12 Indirect Addr 12 FSR0 Reg FSR reg FSR reg STATUS Reg STATUS reg STATUS reg MUX MUX MUX 2010 Microchip Technology Inc. ...
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... Section 11.0 “Data EEPROM and Flash Program Memory Control”. TABLE 3-1: DEVICE SIZES AND ADDRESSES Device PIC12F/LF1822/16F/LF1823 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 The following features are associated with access and control of program memory and data memory: memory in • PCL and PCLATH • ...
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... If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used. 7FFFh Preliminary RETLW INSTRUCTION ;Add Index ;program counter to ;select data ;Index0 data ;Index1 data DATA_INDEX 2010 Microchip Technology Inc. ...
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... File Select Registers (FSR). See Section 3.5 Addressing” for more information. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 3.2.1 CORE REGISTERS The core registers contain the registers that directly affect the basic PIC12F/LF1822/16F/LF1823 ...
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... Note 1: The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction. R-1/q R-1/q R/W-0 Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition (1) Preliminary R/W-0/u R/W-0/u (1) ( bit 0 2010 Microchip Technology Inc. ...
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... General Purpose RAM (80 bytes maximum) 6Fh 70h Common RAM (16 bytes) 7Fh 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 3.2.5 DEVICE MEMORY MAPS The memory maps for the device family are as shown in Table 3-2. TABLE 3-2: MEMORY MAP TABLES Device PIC12F/LF1822/16F/LF1823 ...
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TABLE 3-3: PIC12F/LF1822/PIC16F/LF1823 MEMORY MAP, BANKS 0-7 BANK0 BANK1 000h INDF0 080h INDF0 100h 001h INDF1 081h INDF1 101h 002h PCL 082h PCL 102h 003h STATUS 083h STATUS 103h 004h FSR0L 084h FSR0L 104h 005h FSR0H 085h FSR0H 105h 006h ...
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TABLE 3-4: PIC12F/LF1822/16F/LF1823 MEMORY MAP, BANKS 8-15 BANK 8 BANK 9 INDF0 INDF0 400h 480h 500h INDF1 INDF1 401h 481h 501h PCL PCL 402h 482h 502h STATUS STATUS 403h 483h 503h FSR0L FSR0L 404h 484h 504h FSR0H FSR0H 405h 485h ...
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TABLE 3-5: PIC12F/LF1822/16F/LF1823 MEMORY MAP, BANKS 16-23 BANK16 BANK17 800h INDF0 880h INDF0 900h 801h INDF1 881h INDF1 901h 802h PCL 882h PCL 902h 803h STATUS 883h STATUS 903h 804h FSR0L 884h FSR0L 904h 805h FSR0H 885h FSR0H 905h 806h ...
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TABLE 3-6: PIC12F/LF1822/16F/LF1823 MEMORY MAP, BANKS 24-31 BANK 24 BANK 25 C00h INDF0 C80h INDF0 D00h C01h INDF1 C81h INDF1 D01h C02h PCL C82h PCL D02h C03h STATUS C83h STATUS D03h C04h FSR0L C84h FSR0L D04h C05h FSR0H C85h FSR0H ...
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... FEDh STKPTR FEEh TOSL FEFh TOSH Legend: = Unimplemented data memory locations, read as ‘0’. DS41413A-page 30 3.2.6 SPECIAL FUNCTION REGISTERS SUMMARY The Special Function Register Summary for the device family are as follows: Device PIC12F/LF1822/16F/LF1823 Preliminary 2010 Microchip Technology Inc. Bank(s) Page No ...
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... CPSCON1 — — Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: PIC16F/LF1823 only. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
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... SWDTEN --01 0110 --01 0110 --00 0000 --00 0000 SCS<1:0> 0011 1-00 0011 1-00 LFIOFR HFIOFS 10q0 0q00 qqqq qq0q xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu GO/DONE ADON -000 0000 -000 0000 ADPREF<1:0> 0000 --00 0000 --00 — — 2010 Microchip Technology Inc. ...
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... Unimplemented 11Fh — Unimplemented Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: PIC16F/LF1823 only. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
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... OERR RX9D 0000 000x 0000 000x TRMT TX9D 0000 0010 0000 0010 WUE ABDEN 01-0 0-00 01-0 0-00 2010 Microchip Technology Inc. ...
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... Unimplemented 21Fh — Unimplemented Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: PIC16F/LF1823 only. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
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... PSS1BD<1:0> 0000 0000 0000 0000 STR1B STR1A ---0 0001 ---0 0001 — — — — — — — — — — — — — — — — — — 2010 Microchip Technology Inc. ...
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... Unimplemented 31Fh — Unimplemented Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: PIC16F/LF1823 only. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
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... CLKRDIV<2:0> 0011 0000 0011 0000 — — — MDBIT 0010 ---0 0010 ---0 x--- xxxx u--- uuuu xxx- xxxx uuu- uuuu xxx- xxxx uuu- uuuu 2010 Microchip Technology Inc. ...
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... Unimplemented 41Fh — Unimplemented Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: PIC16F/LF1823 only. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
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... INTF IOCIF 0000 000x 0000 000u — — 2010 Microchip Technology Inc. ...
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... Top-of-Stack High byte TOSH Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: PIC16F/LF1823 only. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
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... If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will 0 be loaded with the address BRW If using BRA, the entire PC will be loaded with the signed value of the operand of the BRA instruction. 0 BRA Preliminary 2010 Microchip Technology Inc. ...
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... RETFIE instructions or the vectoring to an interrupt address. FIGURE 3-4: ACCESSING THE STACK EXAMPLE 1 TOSH:TOSL TOSH:TOSL 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 3.4.1 ACCESSING THE STACK The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack ...
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... Program Counter and pop the stack. 0x09 0x08 0x07 STKPTR = 0x06 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address Preliminary 2010 Microchip Technology Inc. ...
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... The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: • Traditional Data Memory • Linear Data Memory • Program Flash Memory 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 0x0F Return Address 0x0E Return Address ...
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... Not all memory regions are completely implemented. Consult device memory tables for memory limits. DS41413A-page 46 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 Reserved 0x7FFF 0x8000 0x0000 Program Flash Memory 0xFFFF 0x7FFF Preliminary 2010 Microchip Technology Inc. ...
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... FIGURE 3-9: TRADITIONAL DATA MEMORY MAP Direct Addressing From Opcode 4 BSR 6 0 Location Select Bank Select 0000 0x00 0x7F Bank 0 Bank 1 Bank 2 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Indirect Addressing 0 7 FSRxH Bank Select 0001 0010 1111 Bank 31 Preliminary ...
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... FIGURE 3-11: 7 FSRnH 1 0 Location Select 0x020 Bank 0 0x06F 0x0A0 Bank 1 0x0EF 0x120 Bank 2 0x16F 0xF20 Bank 30 0xF6F Preliminary the FSR/INDF interface. All PROGRAM FLASH MEMORY MAP FSRnL 0x8000 0x0000 Program Flash Memory (low 8 bits) 0x7FFF 0xFFFF 2010 Microchip Technology Inc. ...
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... Configuration Word 2, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Preliminary DS41413A-page 49 ...
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... R/P-1/1 R/P-1/1 R/P-1/1 WDTE1 WDTE0 FOSC2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets P = Programmable bit (1) (2) (3) Pin Function Select bit (1) Preliminary R/P-1/1 R/P-1/1 CPD CP bit 7 R/P-1/1 R/P-1/1 FOSC1 FOSC0 bit 0 2010 Microchip Technology Inc. ...
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... Enabling Brown-out Reset does not automatically enable Power-up Timer. 2: The entire data EEPROM will be erased when the code protection is turned off during an erase. 3: The entire program memory will be erased when the code protection is turned off. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Preliminary DS41413A-page 51 ...
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... R/P-1/1 R/P-1/1 — BORV STVREN R-1 U-1 U-1 — — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets P = Programmable bit (1) Preliminary R/P-1/1 U-1 PLLEN — bit 7 R/P-1/1 R/P-1/1 WRT1 WRT0 bit 0 2010 Microchip Technology Inc. ...
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... See Section 11.5 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. For more information on checksum calculation, see the “PIC16F/LF1826/27/PIC12F/LF1822 Memory Programming Specification” (DS41390). 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 “Write such as Preliminary ...
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... Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 13-5 DEV<8:0>: Device ID bits 100111100 = PIC12F1822 100111101 = PIC16F1823 101000100 = PIC12LF1822 101000101 = PIC16LF1823 bit 4-0 REV<4:0>: Revision ID bits These bits are used to identify the revision. Note 1: This location cannot be written. ...
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... Source (MFINTOSC) 31 kHz Source 31 kHz (LFINTOSC) 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 The oscillator module can be configured in one of six clock modes – External clock (ECL, ECM, ECH. See Section 5.2.1.1 “EC Mode”). 2. LP – 32 kHz Low-Power Crystal mode. ...
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... Figure 5-3 and Figure 5-4 show typical circuits for quartz crystal and ceramic resonators, respectively. Preliminary ® MCU design is fully EXTERNAL CLOCK (EC) MODE OPERATION OSC1/CLKIN ® PIC MCU OSC2/CLKOUT (1) 2010 Microchip Technology Inc. ...
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... AN849, “Basic PIC Oscillator Design” (DS00849) ® • AN943, “Practical PIC Oscillator Analysis and Design” (DS00943) • AN949, “Making Your Oscillator Work” (DS00949) 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 FIGURE 5- Internal Logic Sleep C2 Ceramic Resonator Note 1: A series resistor (R ceramic resonators with low drive level ...
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... PIC MCU OSC1/CLKIN Internal Clock OSC2/CLKOUT (1) 100 k, <3V EXT 3 k R 100 k, 3-5V EXT C > 20 pF, 2-5V EXT Output depends upon CLKOUTEN bit of the Configuration Word 1. ) and capacitor (C ) values EXT EXT 2010 Microchip Technology Inc. ...
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... OSCTUNE register (Register 5-3). 3. The LFINTOSC (Low-Frequency Oscillator) is uncalibrated and operates at 31 kHz. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 5.2.2.1 HFINTOSC The High-Frequency Internal Oscillator (HFINTOSC factory calibrated 16 MHz internal clock source. The frequency of the HFINTOSC can be altered via software using the OSCTUNE register (Register 5-3). ...
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... These dupli- cate choices can offer system design trade-offs. Lower power consumption can be obtained when changing oscillator sources for a given frequency. Faster transi- tion times can be obtained between frequency changes that use the same oscillator source. Preliminary 2010 Microchip Technology Inc. ...
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... The 4xPLL is not available for use with the internal oscillator when the SCS bits of the OSCCON register are set to ‘1x’. The SCS bits must be set to ‘00’ to use the 4xPLL with the internal oscilator. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 5.2.2.7 Internal Oscillator Clock Switch ...
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... LFINTOSC HFINTOSC/MFINTOSC LFINTOSC Start-up Time HFINTOSC/ MFINTOSC IRCF <3:0> System Clock DS41413A-page 62 Start-up Time 2-cycle Sync 0 2-cycle Sync LFINTOSC turns off unless WDT or FSCM is enabled 2-cycle Sync 0 Preliminary Running Running Running 2010 Microchip Technology Inc. ...
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... Word 1, or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP modes. The OST does not reflect the status of the Timer1 Oscillator. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 5.3.3 TIMER1 OSCILLATOR The Timer1 Oscillator is a separate crystal oscillator associated with the Timer1 peripheral ...
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... MHz (1) (1) 31.25 kHz-500 kHz (1) 31.25 kHz-16 MHz (1) 31 kHz 32 kHz 16-32 MHz Preliminary Oscillator Delay Oscillator Warm-up Delay (T ) WARM 2 cycles 1 cycle of each 1024 Clock Cycles (OST) 2 s (approx.) 1 cycle of each 1024 Clock Cycles (OST (approx.) 2010 Microchip Technology Inc. ...
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... OSC1 1022 1023 0 1 OSC2 Program Counter System Clock 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 5.4.3 CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC< ...
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... Reset or Sleep). After an appropriate amount of time, the user should check the Status bits in the OSCSTAT register to verify the oscillator start-up and that the system clock switchover has successfully completed. Preliminary 2010 Microchip Technology Inc. ...
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... Clock Output Clock Monitor Output (Q) OSCFIF Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Oscillator Failure Test Test Preliminary Failure ...
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... Timer1 oscillator 00 = Clock determined by FOSC<2:0> in Configuration Word 1 Note 1: Duplicate frequency derived from HFINTOSC. DS41413A-page 68 R/W-1/1 R/W-1/1 IRCF<3:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary U-0 R/W-0/0 R/W-0/0 SCS<1:0> — bit 0 2010 Microchip Technology Inc. ...
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... LFIOFR: Low Frequency Internal Oscillator Ready bit 1 = LFINTOSC is ready 0 = LFINTOSC is not ready bit 0 HFIOFS: High Frequency Internal Oscillator Stable bit 1 = HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 R-0/q R-0/q R-q/q HFIOFR HFIOFL MFIOFR U = Unimplemented bit, read as ‘ ...
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... CONFIG1 7:0 CP MCLRE Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. Note 1: PIC12F1822/16F1823 only. DS41413A-page 70 R/W-0/0 R/W-0/0 R/W-0/0 TUN<5:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Bit 5 Bit 4 ...
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... Upon any device Reset, the reference clock module is disabled. The user’s firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 6.3 Conflicts with the CLKR pin ...
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... R/W-0/0 CLKRDC1 CLKRDC0 CLKRDIV2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (3) (1) (2) /4. See Section 6.3 “Conflicts with the CLKR pin” for details. Preliminary R/W-0/0 R/W-0/0 CLKRDIV1 CLKRDIV0 bit 0 2010 Microchip Technology Inc. ...
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... Bit -/7 Bit -/6 13:8 — — CONFIG1 7:0 CP MCLRE Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Bit 5 Bit 4 Bit 3 Bit 2 CLKRDC0 CLKRDIV2 Bit 13/5 Bit 12/4 Bit 11/3 ...
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... PIC12F/LF1822/16F/LF1823 NOTES: DS41413A-page 74 Preliminary 2010 Microchip Technology Inc. ...
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... SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Programming Mode Exit RESET Instruction Stack Overflow/Underflow Reset Stack Pointer External Reset MCLRE MCLR Sleep WDT Time-out Power-on Reset V DD Brown-out Reset BOR Enable 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 PWRT Zero 64 ms LFINTOSC PWRTEN Preliminary Device Reset DS41413A-page 75 ...
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... BOR protection is unchanged by Sleep. DD Preliminary DD falls below V for a DD BOR , the device BORDC Device Device Operation upon Operation upon wake- up from release of POR Sleep (1) Waits for BOR ready Waits for BOR ready Begins immediately Begins immediately Begins immediately level. DD 2010 Microchip Technology Inc. ...
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... If BOREN <1:0> in Configuration Word BOR Enabled 0 = BOR Disabled bit 6-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 T BORRDY BOR Protection Active (1) T PWRT < T ...
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... Power-up Timer and oscillator start-up timer will expire. Upon bringing MCLR high, the device will begin execution immediately (see Figure 7-4). This is useful for testing purposes or to synchronize more than one device operating in parallel. Preliminary Timer configuration. See 2010 Microchip Technology Inc. ...
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... FIGURE 7-4: RESET START-UP SEQUENCE V DD Internal POR Power-Up Timer MCLR Internal RESET Oscillator Modes External Crystal Oscillator Start-Up Timer Oscillator F OSC Internal Oscillator Oscillator F OSC External Clock (EC) CLKIN F OSC 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 T PWRT T MCLR T OST Preliminary DS41413A-page 79 ...
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... Program Counter 0000h ---1 1000 0000h ---u uuuu 0000h ---1 0uuu 0000h ---0 uuuu ---0 0uuu 0000h ---1 1uuu ( ---1 0uuu 0000h ---u uuuu 0000h ---u uuuu 0000h ---u uuuu Preliminary Condition STATUS PCON Register Register 00-- 110x uu-- 0uuu uu-- 0uuu uu-- uuuu uu-- uuuu 00-- 11u0 uu-- uuuu uu-- u0uu 1u-- uuuu u1-- uuuu 2010 Microchip Technology Inc. ...
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... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 U-0 R/W/HC-1/q R/W/HC-1/q — ...
Page 82
... Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. DS41413A-page 82 Bit 5 Bit 4 Bit 3 Bit 2 — — — — — — RMCLR RI — Preliminary Register Bit 1 Bit 0 on Page — BORRDY 77 POR BOR 101 2010 Microchip Technology Inc. ...
Page 83
... A block diagram of the interrupt logic is shown in Figure 8-1 and Figure 8-2. FIGURE 8-1: INTERRUPT LOGIC TMR0IF TMR0IE From Peripheral Interrupt Logic (Figure 8-2) 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Wake-up (If in Sleep mode) INTF INTE IOCIF IOCIE PEIE GIE ...
Page 84
... PERIPHERAL INTERRUPT LOGIC TMR1GIF TMR1GIE ADIF ADIE RCIF RCIE TXIF TXIE SSPIF SSPIE CCP1IF CCP1IE TMR1IF TMR1IE TMR2IF TMR2IE EEIF EEIE OSFIF OSFIE C1IF C1IE (1) C2IF (1) C2IE BCLIF BCLIE Note 1: PIC16F/LF1823 only. DS41413A-page 84 Preliminary 2010 Microchip Technology Inc. To Interrupt Logic (Figure 8-1) ...
Page 85
... All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 8.2 Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins ...
Page 86
... Inst(PC) NOP NOP PC+1/FSR New PC/ 0004h ADDR PC+1 Inst(PC) NOP NOP PC+1 PC+2 INST(PC) NOP NOP PC+1 PC+2 INST(PC) NOP NOP Preliminary 0005h Inst(0004h) 0005h Inst(0004h) 0004h 0005h NOP Inst(0004h) Inst(0005h) 0004h 0005h NOP NOP Inst(0004h) 2010 Microchip Technology Inc. ...
Page 87
... Latency is the same whether Inst (PC single cycle or a 2-cycle instruction. 3: CLKOUT not available in all oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section 29.0 “Electrical Specifications”. 5: INTF is enabled to be set any time during the Q4-Q1 cycles. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Q2 Q3 ...
Page 88
... Shadow register should be modified and the value will be restored when exiting the ISR. The Shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s appli- cation, other registers may also need to be saved. DS41413A-page 88 Preliminary 2010 Microchip Technology Inc. ...
Page 89
... The INT external interrupt did not occur bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit 1 = When at least one of the interrupt-on-change pins changed state 0 = None of the interrupt-on-change pins have changed state 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register ...
Page 90
... Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 R/W-0/0 TXIE SSP1IE CCP1IE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 TMR2IE TMR1IE bit 0 2010 Microchip Technology Inc. ...
Page 91
... Enables the MSSP Bus Collision Interrupt 0 = Disables the MSSP Bus Collision Interrupt bit 2-0 Unimplemented: Read as ‘0’ Note 1: PIC16F/LF1823 only. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 ...
Page 92
... R-0/0 R/W-0/0 R/W-0/0 TXIF SSP1IF CCP1IF U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary 2010 Microchip Technology Inc. should ensure the R/W-0/0 R/W-0/0 TMR2IF TMR1IF bit 0 ...
Page 93
... Interrupt is pending 0 = Interrupt is not pending bit 2-0 Unimplemented: Read as ‘0’ Note 1: PIC16F/LF1823 only. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. ...
Page 94
... PS2 RCIE TXIE SSP1IE CCP1IE C1IE EEIE BCL1IE — RCIF TXIF SSP1IF CCP1IF C1IF EEIF BCL1IF — Preliminary Register Bit 1 Bit 0 on Page INTF IOCIF 89 PS1 PS0 171 TMR2IE TMR1IE 90 — — 91 TMR2IF TMR1IF 92 — — 93 2010 Microchip Technology Inc. ...
Page 95
... Section 16.0 “Digital-to-Analog Converter (DAC) Module” and Section 14.0 “Fixed Voltage Reference (FVR)” for more information on these modules. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 9.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1 ...
Page 96
... SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP OST (3) T (4) Interrupt Latency Processor in Sleep Inst( Dummy Cycle Inst( Preliminary 0004h 0005h Inst(0004h) Inst(0005h) Dummy Cycle Inst(0004h) 2010 Microchip Technology Inc. ...
Page 97
... C2IF STATUS — — WDTCON — — WDTPS4 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in Power-down mode. Note 1: PIC16F/LF1823 only. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Bit 5 Bit 4 Bit 3 Bit 2 INTE IOCIE TMR0IF IOCAF4 IOCAF3 IOCAF2 IOCAN4 ...
Page 98
... PIC12F/LF1822/16F/LF1823 NOTES: DS41413A-page 98 Preliminary 2010 Microchip Technology Inc. ...
Page 99
... Configurable time-out period is from 268 seconds (typical) • Multiple Reset conditions • Operation during Sleep FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> SWDTEN WDTE<1:0> WDTE<1:0> Sleep 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 23-bit Programmable LFINTOSC Prescaler WDT WDTPS<4:0> Preliminary WDT Time-out DS41413A-page 99 ...
Page 100
... STATUS register are changed to indicate the Active event. See Section 3.0 “Memory Organization” and Active The STATUS register information. Disabled Active Disabled Disabled Preliminary (Register 3-1) for more WDT Cleared Cleared until the end of OST Unaffected 2010 Microchip Technology Inc. ...
Page 101
... SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 00: This bit is ignored. If WDTE<1:0> WDT is turned WDT is turned off If WDTE<1:0> = 1x: This bit is ignored. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 R/W-1/1 R/W-0/0 R/W-1/1 WDTPS3 WDTPS2 WDTPS1 U = Unimplemented bit, read as ‘0’ -m/n = Value at POR and BOR/Value at all other Resets ...
Page 102
... PIC12F/LF1822/16F/LF1823 NOTES: DS41413A-page 102 Preliminary 2010 Microchip Technology Inc. ...
Page 103
... When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 11.1 EEADRL and EEADRH Registers The EEADRH:EEADRL register pair can address maximum of 256 bytes of data EEPROM maximum of 32K words of program memory ...
Page 104
... CPU is able to read and write data to the data EEPROM recommended to code-protect the pro- gram memory when code-protecting data memory. This prevents anyone from replacing your program with a program that will access the contents of the data EEPROM. Preliminary 2010 Microchip Technology Inc. ...
Page 105
... FLASH PROGRAM MEMORY READ CYCLE EXECUTION Flash ADDR Flash Data INSTR (PC) INSTR( BSF EECON1,RD executed here executed here RD bit EEDATH EEDATL Register EERHLT 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 EEADRH,EEADRL PC+3 INSTR ( EEDATH,EEDATL INSTR ( INSTR( Forced NOP executed here executed here Preliminary INSTR ( ...
Page 106
... NOPs. This prevents the user from executing a two-cycle instruction after the RD bit is set. 2: Flash program memory can be read regardless of the setting of the CP bit. Number of Boundary 16 words, = 0000 Preliminary instruction on the next 2010 Microchip Technology Inc. ...
Page 107
... NOP ; Executed (Figure 11-1) NOP ; Ignored (Figure 11-1) BSF INTCON,GIE ; Restore interrupts MOVF EEDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Preliminary DS41413A-page 107 ...
Page 108
... Example 11-5. The initial address is loaded into the EEADRH:EEADRL register pair; the eight words of data are loaded using indirect address- ing. Note: The code Example 11-5 must be repeated multiple times to fully program an erased program memory row. Preliminary 2010 Microchip Technology Inc. sequence provided in ...
Page 109
... EEADRL<3:0> = 0000 EEADRL<3:0> = 0001 Buffer Register 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 continue to run. The processor does not stall when LWLO = 1, loading the write latches. After the write cycle, the processor will resume operation with the third instruction after the EECON1 write instruction. ...
Page 110
... Write AAh ; Set WR bit to begin erase ; Any instructions here are ignored as processor ; halts to begin erase sequence ; Processor will stop here and wait for erase complete. ; after erase processor continues with 3rd instruction ; Disable writes ; Enable interrupts Preliminary 2010 Microchip Technology Inc. ...
Page 111
... EECON2 MOVLW 0AAh MOVWF EECON2 BSF EECON1,WR NOP NOP BCF EECON1,WREN BSF INTCON,GIE 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 ; Disable ints so required sequences will execute properly ; Bank 3 ; Load initial address ; ; ; ; Load initial data address ; ; ; Point to program memory ; Not configuration space ; Enable writes ...
Page 112
... Different access may exist for reads and writes. Refer to Table 11-2. When read access is initiated on an address outside the parameters listed in Table 11-2, the EEDATH:EED- ATL register pair is cleared. Function Read Access User IDs Yes Yes Yes Preliminary Write Access Yes No No 2010 Microchip Technology Inc. ...
Page 113
... EEPROM WRITE VERIFY BANKSEL EEDATL ; MOVF EEDATL, W ;EEDATL not changed ;from previous write BSF EECON1, RD ;YES, Read the ;value written XORWF EEDATL BTFSS STATUS, Z ;Is data the same GOTO WRITE_ERR ;No, handle error : ;Yes, continue 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Preliminary DS41413A-page 113 ...
Page 114
... Value at POR and BOR/Value at all other Resets R/W-0/0 R/W-0/0 R/W-0/0 EEADR<14:8> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u bit 0 R/W-x/u R/W-x/u bit 0 R/W-0/0 R/W-0/0 bit 0 R/W-0/0 R/W-0/0 bit 0 2010 Microchip Technology Inc. ...
Page 115
... RD: Read Control bit 1 = Initiates an program Flash or data EEPROM read. Read takes one cycle cleared in hardware. The RD bit can only be set (not cleared) in software Does not initiate a program Flash or data EEPROM data read. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 R/W/HC-0/0 R/W-x/q R/W-0/0 ...
Page 116
... WREN EEADRL<7:0> EEADRH<6:0 EEDATL<7:0> EEDATH<5:0> INTE IOCIE TMR0IF EEIE BCL1IE — EEIF BCL1IF — Preliminary W-0/0 W-0/0 bit 0 Register Bit 1 Bit 0 on Page WR RD 115 116* 114 114 114 114 INTF IOCIF 89 — — 91 — — 93 2010 Microchip Technology Inc. ...
Page 117
... Write PORTx CK Data Register Data Bus Read PORTx To peripherals ANSELx 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 12.1 Alternate Pin Function The Alternate Pin Function Control (APFCON) registers are used to steer specific peripheral input and output functions between different pins. The APFCON registers are shown in Register 12-1 ...
Page 118
... CCP1/P1A function is on RA5 For 14 Pin Devices (PIC16F/LF1823): CCP1/P1A function is always on RC5 DS41413A-page 118 U-0 R/W-0/0 R/W-0/0 T1GSEL TXCKSEL — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary 2010 Microchip Technology Inc. R/W-0/0 R/W-0/0 P1BSEL CCP1SEL bit 0 ...
Page 119
... INITIALIZING PORTA BANKSEL PORTA ; CLRF PORTA ;Init PORTA BANKSEL LATA ;Data Latch CLRF LATA ; BANKSEL ANSELA ; CLRF ANSELA ;digital I/O BANKSEL TRISA ; MOVLW B'00111000' ;Set RA<5:3> as inputs MOVWF TRISA ;and set RA<2:0> as ;outputs 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Preliminary DS41413A-page 119 ...
Page 120
... CCP1/P1A (PIC12F/LF1822 only) DS41413A-page 120 RA3 No output priorities. Input only pin. RA4 1. OSC2 2. CLKOUT 3. T1OSO 4. CLKR 5. TX/CK (PIC12F/LF1822 only) 6. SDO 7. P1B (PIC12F/LF1822 only) RA5 1. OSC1 2. T1OSI (Timer1 Oscillator) 3. SRNQ (PIC12F/LF1822 only) 4. RX/DT (PIC12F/LF1822 only) 5. CCP1/P1A (PIC12F/LF1822 only) Preliminary 2010 Microchip Technology Inc. ...
Page 121
... TRISA3: RA3 Port Tri-State Control bit This bit is always ‘1’ as RA3 is an input only bit 2-0 TRISA<2:0>: PORTA Tri-State Control bits 1 = PORTA pin configured as an input (tri-stated PORTA pin configured as an output 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 R/W-x/x R-x/x R/W-x/x RA4 ...
Page 122
... R/W-1/1 ANSA4 — ANSA2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) . Digital input buffer disabled. (1) . Digital input buffer disabled. Preliminary R/W-x/u R/W-x/u LATA1 LATA0 bit 0 R/W-1/1 R/W-1/1 ANSA1 ANSA0 bit 0 2010 Microchip Technology Inc. ...
Page 123
... CONFIG1 7:0 CP MCLRE Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA. Note 1: PIC12F1822/16F1823 only. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 R/W-1/1 R/W-1/1 R/W-1/1 WPUA4 WPUA3 WPUA2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 124
... Certain digital input functions override other port functions and are included in the priority list. RC0 1. SCL (MSSP) 2. SCK (MSSP) RC1 1. SDA (MSSP) RC2 1. SDO (MSSP) 2. P1D RC3 1. P1C RC4 1. MDOUT 2. SRNQ 3. C2OUT 4. TX/CK 5. P1B RC5 1. RX/DT 2. CCP1/P1A Preliminary 2010 Microchip Technology Inc. ...
Page 125
... Unimplemented: Read as ‘0’ bit 5-0 LATC<5:0>: PORTC Output Latch Value bits Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is return of actual I/O pin values. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 R/W-x/u R/W-x/u R/W-x/u RC4 RC3 RC2 U = Unimplemented bit, read as ‘ ...
Page 126
... WPUC3 WPUC2 Preliminary R/W-1/1 R/W-1/1 ANSC1 ANSC0 bit 0 R/W-1/1 R/W-1/1 WPUC1 WPUC0 bit 0 (1) Register Bit 1 Bit 0 on Page ANSC1 ANSC0 126 LATC1 LATC0 125 PS<2:0> 171 RC1 RC0 125 TRISC1 TRISC0 125 WPUC1 WPUC0 126 2010 Microchip Technology Inc. ...
Page 127
... R RAx IOCAPx 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 13.3 Interrupt Flags The IOCAFx bits located in the IOCAF register are status flags that correspond to the Interrupt-on-change pins of PORTA expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set ...
Page 128
... R/W/HS-0/0 IOCAF4 IOCAF3 IOCAF2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets HS - Bit is set in hardware Preliminary R/W-0/0 R/W-0/0 IOCAP1 IOCAP0 bit 0 R/W-0/0 R/W-0/0 IOCAN1 IOCAN0 bit 0 R/W/HS-0/0 R/W/HS-0/0 IOCAF1 IOCAF0 bit 0 2010 Microchip Technology Inc. ...
Page 129
... IOCAN — — IOCAP — — TRISA — — Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupt-on-Change. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Bit 5 Bit 4 Bit 3 Bit 2 — ANSA4 — ANSA2 TMR0IE INTE IOCIE ...
Page 130
... PIC12F/LF1822/16F/LF1823 NOTES: DS41413A-page 130 Preliminary 2010 Microchip Technology Inc. ...
Page 131
... FVRCON register. FIGURE 14-1: VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> CDAFVR<1:0> FVREN FVRRDY 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 14.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC, Comparators, and DAC is routed through two independent programmable gain amplifiers. Each , with 1 ...
Page 132
... ADC Fixed Voltage Reference Peripheral output is 1x (1.024V ADC Fixed Voltage Reference Peripheral output is 2x (2.048V ADC Fixed Voltage Reference Peripheral output is 4x (4.096V) Note 1: FVRRDY is always ‘1’ on devices with the LDO (PIC12F1822/16F1823). 2: Fixed Voltage Reference output cannot exceed V TABLE 14-1: ...
Page 133
... AN7 DAC FVR Buffer1 CHS<4:0> Note 1: When ADON = 0, all multiplexer inputs are disconnected. 2: Not available on PIC12F/LF1822. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. (ADC) ...
Page 134
... Table 15-1 gives examples of appro- priate ADC clock selections. Note: Unless using the F system clock frequency will change the ADC adversely affect the ADC result. Preliminary peri- AD specifica any changes in the RC clock frequency, which may 2010 Microchip Technology Inc. ...
Page 135
... Sleep mode. FIGURE 15-2: ANALOG-TO-DIGITAL CONVERSION Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 ) V . DEVICE OPERATING FREQUENCIES AD S Device Frequency (F Device Frequency (F 20 MHz 16 MHz (2) (2) (2) 100 ns 125 ns (2) (2) (2) 200 ns ...
Page 136
... ADCON1 register controls the output format. Figure 15-3 shows the two output formats. ADRESH LSB bit 0 bit 7 10-bit A/D Result MSB bit 0 bit 7 10-bit A/D Result Preliminary ADRESL bit 0 Unimplemented: Read as ‘0’ LSB bit 0 2010 Microchip Technology Inc. ...
Page 137
... Note: A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 15.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the F option ...
Page 138
... MOVF ADRESL,W MOVWF RESULTLO Preliminary A/D CONVERSION ; ;clock ;Vdd and Vss Vref ; ;Set RA0 to input ; ;Set RA0 to analog ; ;Turn ADC On ;Acquisiton delay ;No, test again ; ;Read upper 2 bits ;store in GPR space ; ;Read lower 8 bits ;Store in GPR space 2010 Microchip Technology Inc. ...
Page 139
... PIC16F/LF1823 only. For PIC12F/LF1822 it is “Reserved. No channel connected”. 2: See Section 16.0 “Digital-to-Analog Converter (DAC) Module” for more information. 3: See Section 14.0 “Fixed Voltage Reference (FVR)” for more information. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 R/W-0/0 R/W-0/0 R/W-0/0 CHS2 ...
Page 140
... V REF connected to internal fixed voltage reference REF DS41413A-page 140 R/W-0/0 U-0 U-0 ADCS0 — — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets DD + REF Preliminary R/W-0/0 R/W-0/0 ADPREF1 ADPREF0 bit 0 2010 Microchip Technology Inc. ...
Page 141
... Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result bit 5-0 Reserved: Do not use. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 R/W-x/u R/W-x/u R/W-x/u ADRES6 ADRES5 ADRES4 U = Unimplemented bit, read as ‘0’ ...
Page 142
... Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u ADRES4 ADRES3 ADRES2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u ADRES9 ADRES8 bit 0 R/W-x/u R/W-x/u ADRES1 ADRES0 bit 0 2010 Microchip Technology Inc. ...
Page 143
... REF 2: The charge holding capacitor (C 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started ...
Page 144
... V SS DS41413A-page 144 V DD Sampling Switch 0. Rss R IC LEAKAGE (1) I 0. Full-Scale Range 1 LSB ideal Full-Scale Transition Analog Input Voltage 1 LSB ideal Zero-Scale V REF Transition Preliminary HOLD REF Sampling Switch (k) 2010 Microchip Technology Inc. ...
Page 145
... TRISC — — Legend: — = unimplemented read as ‘0’. Shaded cells are not used for ADC module. * Page provides register information. Note 1: PIC16F/LF1823 only. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Bit 5 Bit 4 Bit 3 Bit 2 CHS3 CHS2 CHS1 CHS0 ADCS1 ADCS0 — ...
Page 146
... PIC12F/LF1822/16F/LF1823 NOTES: DS41413A-page 146 Preliminary 2010 Microchip Technology Inc. ...
Page 147
... SRC The negative voltage source is disabled by setting the DACLPS bit in the DACCON0 register. Clearing the DACLPS bit in the DACCON0 register disables the positive voltage source. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 16.3.1 OUTPUT CLAMPED TO POSITIVE VOLTAGE SOURCE The DAC output voltage can be set to V ...
Page 148
... Output Clamped to Positive Voltage Source V + SRC R DACR<4:0> = 11111 R DACEN = 0 DACLPS = 1 DAC Voltage Ladder (see Figure 16- SRC DS41413A-page 148 Output Clamped to Positive Voltage Source V + SRC R R DACEN = 0 DACLPS = SRC Preliminary 2010 Microchip Technology Inc. DAC Voltage Ladder (see Figure 16-2) DACR<4:0> = 00000 ...
Page 149
... DAC voltage reference output for external connections to DACOUT. Figure 16-3 shows an example buffering technique. FIGURE 16-2: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM FVR BUFFER2 REF DACPSS<1:0> 2 DACEN DACLPS V - REF V SS 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Digital-to-Analog Converter (DAC SRC Steps SRC Preliminary DACR< ...
Page 150
... Effects of a Reset A device Reset affects the following: • DAC is disabled. • DAC output voltage is removed from the DACOUT pin. • The DACR<4:0> range select bits are cleared. DS41413A-page 150 + DACOUT – Preliminary Buffered DAC Output 2010 Microchip Technology Inc. ...
Page 151
... OUT SRC SRC Note 1: The output select bits are always right justified to ensure that any number of bits can be used without affecting the register layout. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 U-0 R/W-0/0 R/W-0/0 — DACPSS<1:0> Unimplemented bit, read as ‘0’ ...
Page 152
... Shaded cells are unused by the DAC module. DS41413A-page 152 Bit 5 Bit 4 Bit 3 Bit 2 Reserved Reserved CDAFVR1 CDAFVR0 DACOE — DACPSS1 DACPSS0 — DACR4 DACR3 DACR2 Preliminary Register Bit 1 Bit 0 on page ADFVR1 ADFVR0 132 — — 151 DACR1 DACR0 151 2010 Microchip Technology Inc. ...
Page 153
... Note: Enabling both the Set and Reset inputs from any one source at the same time may result in indeterminate operation, as the Reset dominance cannot be assured. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 17.2 Latch Output The SRQEN and SRNQEN bits of the SRCON0 regis- ter control the Q and Q latch outputs ...
Page 154
... SYNCC2OUT (4) SRRC2E (3) SYNCC1OUT SRRC1E Note and simultaneously Pulse generator causes a 1 Q-state pulse width. 3: Name denotes the connection point at the comparator output. 4: PIC16F/LF1823 only. DS41413A-page 154 SRLEN SRQEN (1) Latch R Q SRLEN SRNQEN Preliminary 2010 Microchip Technology Inc. SRQ SRNQ ...
Page 155
... Pulse set input for 1 Q-clock period effect on set input. bit 0 SRPR: Pulse Reset Input of the SR Latch bit 1 = Pulse reset input for 1 Q-clock period effect on reset input. Note 1: Set only, always reads back ‘0’. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 MHz MHz OSC OSC 39 ...
Page 156
... C1 Comparator output has no effect on the reset input of the SR Latch Note 1: PIC16F/LF1823 only. DS41413A-page 156 R/W-0/0 R/W-0/0 R/W-0/0 (1) SRSC1E SRRPE SRRCKE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) (1) Preliminary R/W-0/0 R/W-0/0 (1) SRRC2E SRRC1E bit 0 2010 Microchip Technology Inc. ...
Page 157
... SRLEN SRCLK2 SRCON1 SRSPE SRSCKE TRISA — — Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the SR Latch module. Note 1: PIC16F/LF1823 only. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Bit 5 Bit 4 Bit 3 Bit 2 — ANSA4 ANSA3 ANSA2 SRCLK1 SRCLK0 SRQEN ...
Page 158
... PIC12F/LF1822/16F/LF1823 NOTES: DS41413A-page 158 Preliminary 2010 Microchip Technology Inc. ...
Page 159
... When the analog voltage greater than the analog voltage the output of the comparator is a digital high level. IN The PIC12F/LF1822 devices contain one comparator, while the PIC16F/LF1823 devices contain two. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 FIGURE 18- ...
Page 160
... Output of comparator can be frozen during debugging. DS41413A-page 160 (1) Interrupt Interrupt C1POL D ( (from Timer1) T1CLK Preliminary C1INTP det Set C1IF C1INTN det C1OUT To Data Bus Q MC1OUT To ECCP PWM Logic C1SYNC C1OE TRIS bit C1OUT Timer1 or SR Latch SYNCC1OUT 2010 Microchip Technology Inc. ...
Page 161
... FVR Buffer2 3 CxON PCH<1:0> Note 1: When CxON = 0, the Comparator will produce a ‘0’ at the output. 2: When CxON = 0, all multiplexer inputs are disconnected. 3: Output of comparator can be frozen during debugging. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 (1) Interrupt Interrupt C POL CxHYS D (from Timer1) ...
Page 162
... CxSP control bit. The default state for this bit is ‘1’ which selects the normal speed mode. Device power consumption can be optimized at the cost of slower comparator propaga- tion delay by clearing the CxSP bit to ‘0’. Preliminary 2010 Microchip Technology Inc. CxOUT ...
Page 163
... Timer1 clock source and Timer1 increments on the rising edge of its clock source. See the Comparator Block Diagram (Figure ) and the Timer1 Block Diagram (Figure 20-1) for more information. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 18.5 Comparator Interrupt An interrupt can be generated upon a change in the ...
Page 164
... Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified 0. (1) I LEAKAGE 0. Vss Preliminary and V . The DD SS and Comparator 2010 Microchip Technology Inc. ...
Page 165
... CxSYNC: Comparator Output Synchronous Mode bit 1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source Comparator output to Timer1 and I/O pin is asynchronous. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 R/W-0/0 U-0 R/W-1/1 ...
Page 166
... Value at POR and BOR/Value at all other Resets U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary R/W-0/0 R/W-0/0 (1) CxNCH1 CxNCH0 bit 0 R-0/0 R-0/0 (1) MC2OUT MC1OUT bit 0 2010 Microchip Technology Inc. ...
Page 167
... C2IF PIR2 TRISA — — (1) TRISC — — Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module. Note 1: PIC16F/LF1823 only. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Bit 5 Bit 4 Bit 3 Bit 2 — ANSA4 ANSA3 ANSA2 C1OE C1POL — ...
Page 168
... PIC12F/LF1822/16F/LF1823 NOTES: DS41413A-page 168 Preliminary 2010 Microchip Technology Inc. ...
Page 169
... From CPSCLK 1 TMR0CS TMR0SE T0XCS 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 19.1.2 8-BIT COUNTER MODE In 8-bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin or the Capacitive Sensing Oscillator (CPSCLK) signal. 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION register to ‘ ...
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... Section 29.0 “Electrical Specifications”. 19.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. DS41413A-page 170 Preliminary 2010 Microchip Technology Inc. ...
Page 171
... Timer0 Module Register TRISA — — Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Timer0 module. * Page provides register information. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 R/W-1/1 R/W-1/1 R/W-1/1 TMR0SE PSA U = Unimplemented bit, read as ‘0’ ...
Page 172
... T1CKPS<1:0> F OSC 01 Internal Clock F /4 OSC 00 Internal Clock Preliminary 0 Data Bus T1GVAL T1GCON Q1 EN Interrupt Set TMR1GIF det TMR1GE To Comparator Module Synchronized 0 clock input 1 (3) Synchronize det OSC Sleep input Internal Clock To Clock Switching Modules 2010 Microchip Technology Inc. ...
Page 173
... Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 20.2 Clock Source Selection The TMR1CS<1:0> and T1OSCEN bits of the T1CON register are used to select the clock source for Timer1. Table 20-2 displays the clock source selections. 20.2.1 INTERNAL CLOCK SOURCE When the internal clock source is selected the ...
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... Timer1 Gate Source Timer1 Gate Pin 00 Overflow of Timer0 01 (TMR0 increments from FFh to 00h) Comparator 1 Output SYNCC1OUT 10 (optionally Timer1 synchronized output) Comparator 2 Output SYNCC2OUT 11 (optionally Timer1 synchronized output) Preliminary 2010 Microchip Technology Inc. Timer1 Operation Counts 0 Holds Count 1 Holds Count 0 Counts 1 ...
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... Note: Enabling Toggle mode at the same time as changing the gate polarity may result in indeterminate operation. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 20.6.4 TIMER1 GATE SINGLE-PULSE MODE When Timer1 Gate Single-Pulse mode is enabled possible to capture a single pulse gate event. Timer1 Gate Single-Pulse mode is first enabled by setting the T1GSPM bit in the T1GCON register ...
Page 176
... Special Event Trigger to be missed. In the event that a write to TMR1H or TMR1L coincides with a Special Event Trigger from the CCP, the write will take precedence. For more information, see Section 15.2.5 “Special Event Trigger”. Preliminary 2010 Microchip Technology Inc. see Section 23.0 /4 should be OSC ...
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... FIGURE 20-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 N FIGURE 20-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL Timer1 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Preliminary DS41413A-page 177 ...
Page 178
... TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF DS41413A-page 178 Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL Preliminary 2010 Microchip Technology Inc. Cleared by software ...
Page 179
... TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Set by hardware on falling edge of T1GVAL Preliminary Cleared by hardware on falling edge of T1GVAL Cleared by software DS41413A-page 179 ...
Page 180
... Enables Timer1 0 = Stops Timer1 Clears Timer1 Gate flip-flop DS41413A-page 180 R/W-0/u R/W-0/u R/W-0/u T1OSCEN T1SYNC U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ) OSC /4) OSC ) OSC Preliminary U-0 R/W-0/u — TMR1ON bit 0 2010 Microchip Technology Inc. ...
Page 181
... Unaffected by Timer1 Gate Enable (TMR1GE). bit 1-0 T1GSS<1:0>: Timer1 Gate Source Select bits 00 = Timer1 Gate pin 01 = Timer0 overflow output 10 = Comparator 1 optionally synchronized output (SYNCC1OUT Comparator 2 optionally synchronized output (SYNCC2OUT) Note 1: PIC16F/LF1823 only. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 R/W-0/u R/W/HC-0/u R-x/x T1GSPM T1GGO/ T1GVAL DONE U = Unimplemented bit, read as ‘ ...
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... TRISA5 TRISA4 TRISA3 TRISA2 T1GTM T1GSPM T1GGO/ T1GVAL DONE Preliminary Register Bit 1 Bit 0 on Page ANSA1 ANSA0 122 221 INTF IOCIF 89 TMR2IE TMR1IE 90 TMR2IF TMR1IF 92 172* 172* TRISA1 TRISA0 121 — TMR1ON 180 T1GSS1 T1GSS0 181 2010 Microchip Technology Inc. ...
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... NOTES: 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Preliminary DS41413A-page 183 ...
Page 184
... See Figure 21-1 for a block diagram of Timer2. FIGURE 21-1: TIMER2 BLOCK DIAGRAM Prescaler F /4 OSC 1:1, 1:4, 1:16, 1:64 2 T2CKPS<1:0> DS41413A-page 184 TMRx Outp2t Reset TMR2 Postscaler Comparator 1 PR2 T2OUTPS<3:0> Preliminary Sets Flag bit TMR2IF 2010 Microchip Technology Inc. ...
Page 185
... TMR2 Match Interrupt Enable bit, TMR2IE of the PIE1 register. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0>, of the T2CON register. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 21.3 Timer2 Output The unscaled output of TMR2 is available primarily to the CCP1 module, where it is used as a time base for operations in PWM mode ...
Page 186
... T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler Prescaler is 64 DS41413A-page 186 R/W-0/0 R/W-0/0 R/W-0/0 TMR2ON U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 T2CKPS<1:0> bit 0 2010 Microchip Technology Inc. ...
Page 187
... T2CON — TMR2 Holding Register for the 8-bit TMR2 Register Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module. * Page provides register information. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Bit 5 Bit 4 Bit 3 Bit 2 DC1B<1:0> TMR0IE ...
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... PIC12F/LF1822/16F/LF1823 NOTES: DS41413A-page 188 Preliminary 2010 Microchip Technology Inc. ...
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... No Channel Selected * * 1111 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Using this method, the DSM can generate the following types of Key Modulation schemes: • Frequency-Shift Keying (FSK) • Phase-Shift Keying (PSK) • On-Off Keying (OOK) Additionally, the following features are provided within the DSM module: • ...
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... MDCHSYNC bit in the MDCARH register. Synchroniza- tion for the carrier low signal can be enabled by setting the MDCLSYNC bit in the MDCARL register. Figure 22-1 through Figure 22-5 show timing diagrams of using various synchronization methods. Preliminary 2010 Microchip Technology Inc. ...
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... Active Carrier State FIGURE 22-3: CARRIER HIGH SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 0) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 0 CARH Active Carrier State 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 CARL CARH CARH CARL both Preliminary CARL both CARL DS41413A-page 191 ...
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... Active Carrier CARH State FIGURE 22-5: FULL SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) Falling edges used to sync MDCHSYNC = 1 MDCLSYNC = 1 Active Carrier CARH State DS41413A-page 192 CARL CARH CARL CARH Preliminary 2010 Microchip Technology Inc. CARL CARL ...
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... The DSM module is not affected by Sleep mode. The DSM can still operate during Sleep, if the Carrier and Modulator input sources are also still operable during Sleep. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 22.12 Effects of a Reset Upon any device Reset, the Data Signal Modulator module is disabled. The user’ ...
Page 194
... MDBIT must be selected as the modulation source in the MDSRC register for this operation. DS41413A-page 194 R/W-0/0 R/W-0/0 U-0 MDOPOL MDOUT — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary U-0 R/W-0/0 — MDBIT bit 0 (1) 2010 Microchip Technology Inc. ...
Page 195
... CCP1 output (PWM Output mode only) 0001 = MDMIN port pin 0000 = MDBIT bit of MDCON register is modulation source Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 U-0 R/W-x/u R/W-x/u — ...
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... Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. DS41413A-page 196 U-0 R/W-x/u R/W-x/u — MDCH<3:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary 2010 Microchip Technology Inc. R/W-x/u R/W-x/u bit 0 (1) ...
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... MDOE MDSRC MDMSODIS — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in the Data Signal Modulator mode. 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 U-0 R/W-x/u — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 198
... PIC12F/LF1822/16F/LF1823 NOTES: DS41413A-page 198 Preliminary 2010 Microchip Technology Inc. ...
Page 199
... The Full-Bridge ECCP module has four available I/O pins, while the Half-Bridge ECCP module only has two. See Table 23-1. TABLE 23-1: PWM RESOURCES Device Name ECCP1 PIC12F/LF1822 Enhanced PWM Half-Bridge PIC16F/LF1823 Enhanced PWM Full-Bridge 2010 Microchip Technology Inc. PIC12F/LF1822/16F/LF1823 Preliminary DS41413A-page 199 ...
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... NEW_CAPT_PS ;Load the W reg with TMR1L MOVWF CCP1CON Preliminary /4) or from an OSC of the CCP1CON register. CHANGING BETWEEN CAPTURE PRESCALERS ;Set Bank bits to point ;to CCP1CON ;Turn CCP1 module off ;the new prescaler ;move value and CCP1 ON ;Load CCP1CON with this ;value 2010 Microchip Technology Inc. ...