PIC18LF8680-I/PT Microchip Technology, PIC18LF8680-I/PT Datasheet - Page 385

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PIC18LF8680-I/PT

Manufacturer Part Number
PIC18LF8680-I/PT
Description
IC, 8BIT MCU, PIC18LF, 40MHZ, PLCC-64
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18LF8680-I/PT

Controller Family/series
PIC18
No. Of I/o's
39
Eeprom Memory Size
1024Byte
Ram Memory Size
3328Byte
Cpu Speed
40MHz
No. Of Timers
4
Core Size
8 Bit
Program Memory Size
32768 Words
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Rohs Compliant
Yes
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3328 B
Interface Type
I2C, SPI, AUSART, CAN
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
69
Number Of Timers
8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF8680-I/PT
Manufacturer:
Microchip
Quantity:
230
Part Number:
PIC18LF8680-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
CPFSGT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2004 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
W
If REG
If REG
No
No
No
Q1
Q1
Q1
PC
PC
=
=
=
=
register ‘f’
operation
operation
operation
Compare f with W, skip if f > W
[ label ] CPFSGT
0
a
(f)
skip if (f) > (W)
(unsigned comparison)
None
Compares the contents of data
memory location ‘f’ to the contents
of the W by performing an
unsigned subtraction.
If the contents of ‘f’ are greater than
the contents of WREG
fetched instruction is discarded and
a NOP is executed instead, making
this a two-cycle instruction. If ‘a’ is
‘0’, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
1
1(2)
Note: 3 cycles if skip and followed
HERE
NGREATER
GREATER
Read
0110
No
No
No
Q2
Q2
Q2
Address (HERE)
?
W;
Address (GREATER)
W;
Address (NGREATER)
f
[0,1]
W),
255
by a 2-word instruction.
010a
operation
operation
operation
CPFSGT REG, 0
:
:
Process
Data
No
No
No
Q3
Q3
Q3
ffff
f [,a]
,
then the
operation
operation
operation
operation
PIC18F6585/8585/6680/8680
No
No
No
No
Q4
Q4
Q4
ffff
CPFSLT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
PC
W
If REG
If REG
Q1
Q1
Q1
PC
PC
=
=
<
=
=
register ‘f’
operation
operation
operation
Compare f with W, skip if f < W
[ label ] CPFSLT
0
a
(f) – W),
skip if (f) < (W)
(unsigned comparison)
None
Compares the contents of data
memory location ‘f’ to the contents
of W by performing an unsigned
subtraction.
If the contents of ‘f’ are less than
the contents of W, then the fetched
instruction is discarded and a NOP
is executed instead, making this a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected. If ’a’
is ‘1’, the BSR will not be overrid-
den (default).
1
1(2)
Note: 3 cycles if skip and followed
HERE
NLESS
LESS
Read
0110
No
No
No
Q2
Q2
Q2
Address (HERE)
?
W;
Address (LESS)
W;
Address (NLESS)
f
[0,1]
255
by a 2-word instruction.
CPFSLT REG, 1
:
:
000a
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
DS30491C-page 383
ffff
f [,a]
operation
operation
operation
operation
No
No
No
No
Q4
Q4
Q4
ffff

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