PIC12LF1822-I/MF Microchip Technology, PIC12LF1822-I/MF Datasheet - Page 309
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PIC12LF1822-I/MF
Manufacturer Part Number
PIC12LF1822-I/MF
Description
IC, 8BIT MCU, PIC12, 32MHZ, DFN-8
Manufacturer
Microchip Technology
Series
PIC® XLP™ 12Fr
Datasheets
1.PIC12F1822T-ISN.pdf
(404 pages)
2.PIC12F1822T-ISN.pdf
(10 pages)
3.PIC12F1822-IMF.pdf
(398 pages)
Specifications of PIC12LF1822-I/MF
Controller Family/series
PIC12
No. Of I/o's
6
Eeprom Memory Size
256Byte
Ram Memory Size
128Byte
Cpu Speed
32MHz
No. Of Timers
3
Core Size
8 Bit
Program Memory Size
3.5KB
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DFN
Processor Series
PIC12LF
Core
PIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12LF1822-I/MF
Manufacturer:
MICROCHIP
Quantity:
3 600
- Current page: 309 of 404
- Download datasheet (4Mb)
FIGURE 26-12:
TABLE 26-8:
2010 Microchip Technology Inc.
BAUDCON
INTCON
PIE1
PIR1
RCREG
RCSTA
SPBRGL
SPBRGH
TRISA
TRISC
TXSTA
Legend:
Note 1:
(SCKP = 0)
(SCKP = 1)
(Interrupt)
Note:
TX/CK pin
TX/CK pin
CREN bit
SREN bit
bit SREN
RCIF bit
RCREG
Name
RX/DT
Write to
Read
(2)
2:
pin
*
— = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Master Reception.
Page provides register information.
PIC12F/LF1822 only.
PIC16F/LF1823 only.
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
‘0’
TMR1GIE
TMR1GIF
ABDOVF
CSRC
SPEN
SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
RECEPTION
Bit 7
GIE
—
—
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
bit 0
RCIDL
ADIE
PEIE
ADIF
Bit 6
RX9
TX9
—
—
PIC12F/LF1822/PIC16F/LF1823
bit 1
TRISA5
TMR0IE
TRISC5
SREN
TXEN
RCIE
RCIF
Bit 5
—
EUSART Receive Data Register
(1)
bit 2
TRISA4
Preliminary
TRISC4
CREN
SYNC
SCKP
INTE
Bit 4
TXIE
TXIF
BRG<15:8>
BRG<7:0>
(1)
bit 3
TRISC3
ADDEN
TRISA3
SENDB
BRG16
SSPIE
SSPIF
IOCIE
Bit 3
bit 4
TMR0IF
CCP1IE
CCP1IF
TRISA2
TRISC2
BRGH
FERR
Bit 2
—
bit 5
TMR2IE
TMR2IF
TRISA1
TRISC1
OERR
TRMT
WUE
Bit 1
INTF
bit 6
TMR1IE
TMR1IF
TRISC0
ABDEN
TRISA0
bit 7
IOCIF
RX9D
TX9D
Bit 0
DS41413B-page 309
Register
on Page
290*
297*
297*
296
101
102
105
295
124
128
294
‘0’
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