ATTINY861A-PU Atmel, ATTINY861A-PU Datasheet - Page 145

IC, MCU, 8BIT, 8K FLASH, 20PDIP

ATTINY861A-PU

Manufacturer Part Number
ATTINY861A-PU
Description
IC, MCU, 8BIT, 8K FLASH, 20PDIP
Manufacturer
Atmel
Datasheet

Specifications of ATTINY861A-PU

Controller Family/series
ATtiny
No. Of I/o's
16
Eeprom Memory Size
512Byte
Ram Memory Size
512Byte
Cpu Speed
20MHz
No.
RoHS Compliant
Core Size
8bit
Program Memory Size
8KB
Oscillator Type
External, Internal
Rohs Compliant
Yes
8197B–AVR–01/10
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. See
15-6. This assures a fixed delay from the trigger event to the start of conversion. In this mode,
the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger
source signal. Three additional CPU clock cycles are used for synchronization logic.
Figure 15-6. ADC Timing Diagram, Auto Triggered Conversion
In Free Running mode (see
conversion completes, while ADSC remains high.
Figure 15-7. ADC Timing Diagram, Free Running Conversion
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
Prescaler
Reset
MUX and REFS
Update
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
1
2
Figure
Conversion
Complete
3
One Conversion
Sample &
Hold
11
4
15-7), a new conversion will be started immediately after the
12
5
6
13
7
One Conversion
Next Conversion
1
Sign and MSB of Result
LSB of Result
8
2
MUX and REFS
Update
9
3
10
Conversion
Complete
Sample & Hold
11
4
12
13
Sign and MSB of Result
LSB of Result
Next Conversion
1
Prescaler
Reset
Figure
2
145

Related parts for ATTINY861A-PU