PIC24FJ256GB106-I/MR Microchip Technology, PIC24FJ256GB106-I/MR Datasheet - Page 238

• Manufacturer Part Number: PIC24FJ256GB106-I/MR
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-64
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256GB106-I/MR

• Controller Family/series: PIC24
• No. Of I/o's: 51
• Ram Memory Size: 16KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Core Size: 16 Bit
• Program Memory Size: 256KB
• Peripherals: ADC, Comparator, PWM, RTC, Timer
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART, USB OTG
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC24FJ256GB110 FAMILY
19.1
The RTCC module registers are organized into three
categories:
• RTCC Control Registers
• RTCC Value Registers
• Alarm Value Registers
19.1.1
To limit the register interface, the RTCC Timer and
Alarm Time registers are accessed through corre-
sponding register pointers. The RTCC Value register
window (RTCVALH and RTCVALL) uses the RTCPTR
bits (RCFGCAL<9:8>) to select the desired Timer
register pair (see Table 19-1).
By writing the RTCVALH byte, the RTCC Pointer value,
RTCPTR<1:0> bits, decrement by one until they reach
‘00’. Once they reach ‘00’, the MINUTES and
SECONDS value will be accessible through RTCVALH
and RTCVALL until the pointer value is manually
changed.
TABLE 19-1:
The Alarm Value register window (ALRMVALH and
ALRMVALL)
(ALCFGRPT<9:8>) to select the desired Alarm register
pair (see Table 19-2).
By writing the ALRMVALH byte, the Alarm Pointer
value, ALRMPTR<1:0> bits, decrement by one until
they reach ‘00’. Once they reach ‘00’, the ALRMMIN
and ALRMSEC value will be accessible through
ALRMVALH and ALRMVALL until the pointer value is
manually changed.
EXAMPLE 19-1:
DS39897B-page 236
asm
asm
asm
asm
asm
asm
RTCPTR
<1:0>
00
01
10
11
volatile("disi #5");
volatile("mov #0x55, w7");
volatile("mov w7, _NVMKEY");
volatile("mov #0xAA, w8");
volatile("mov w8, _NVMKEY");
volatile("bset _RCFGCAL, #13");
RTCC Module Registers
REGISTER MAPPING
uses
RTCVAL<15:8>
RTCVAL REGISTER MAPPING
RTCC Value Register Window
WEEKDAY
MINUTES
MONTH
SETTING THE RTCWREN BIT
—
the
ALRMPTR
RTCVAL<7:0>
SECONDS
HOURS
YEAR
DAY
Preliminary
bits
//set the RTCWREN bit
TABLE 19-2:
Considering that the 16-bit core does not distinguish
between 8-bit and 16-bit read operations, the user must
be aware that when reading either the ALRMVALH or
ALRMVALL bytes will decrement the ALRMPTR<1:0>
value. The same applies to the RTCVALH or RTCVALL
bytes with the RTCPTR<1:0> being decremented.
19.1.2
In order to perform a write to any of the RTCC Timer
registers, the RTCWREN bit (RCFGCAL<13>) must be
set (refer to Example 19-1).
ALRMPTR
Note:
Note:
<1:0>
00
01
10
11
This only applies to read operations and
not write operations.
WRITE LOCK
To avoid accidental writes to the timer, it is
recommended that the RTCWREN bit
(RCFGCAL<13>) is kept clear at any
other time. For the RTCWREN bit to be
set, there is only 1 instruction cycle time
window allowed between the unlock
sequence and the setting of RTCWREN;
therefore, it is recommended that code
follow the procedure in Example 19-1.
For applications written in C, the unlock
sequence should be implemented using
in-line assembly.
ALRMVAL<15:8> ALRMVAL<7:0>
ALRMVAL REGISTER
MAPPING
Alarm Value Register Window
ALRMMNTH
ALRMMIN
ALRMWD
© 2008 Microchip Technology Inc.
—
ALRMSEC
ALRMDAY
ALRMHR
—