PIC32MX775F512L-80I/BG Microchip Technology, PIC32MX775F512L-80I/BG Datasheet - Page 4
![IC, 32BIT MCU, PIC32, 80MHZ, BGA-100](/photos/28/60/286072/pic32mx775f512l-80i_bg_sml.jpg)
PIC32MX775F512L-80I/BG
Manufacturer Part Number
PIC32MX775F512L-80I/BG
Description
IC, 32BIT MCU, PIC32, 80MHZ, BGA-100
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.PIC32MX320F032H-40IPT.pdf
(66 pages)
2.PIC32MX575F256H-80IMR.pdf
(2 pages)
3.PIC32MX575F256H-80IMR.pdf
(254 pages)
4.PIC32MX575F256H-80IMR.pdf
(14 pages)
Specifications of PIC32MX775F512L-80I/BG
Controller Family/series
PIC32
Ram Memory Size
64KB
Cpu Speed
80MHz
No. Of Timers
5
Interface
CAN, I2C, SPI, UART, USB
No. Of Pwm Channels
5
Core Size
32 Bit
Program Memory Size
512 KB
Core Processor
MIPS32® M4K™
Speed
80MHz
Connectivity
CAN, Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
121-TFBGA
Embedded Interface Type
CAN, I2C, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
PIC32MX7xx
Core
MIPS
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX775F512L-80I/BG
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC32MX575/675/695/775/795
Silicon Errata Issues
1. Module: I
DS80480E-page 4
Note:
The I
I
performing a Start condition.
Work around
1.
2.
Affected Silicon Revisions
2
C2, may encounter a bus collision when
A0
X
Use another I
sequence I
Start event.
Connect an unused general-purpose I/O
pin to the SDAx pin of the I
used.
The user software must perform the follow-
ing sequence of operations in order to
execute a Start condition on the I
a)
b)
c)
d)
e)
f)
g)
2
C modules, with the exception of I
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A0).
With the I
LAT bit of the general-purpose I/O pin
that is connected to the SDAx pin.
Then, clear the corresponding TRIS bit
to make sure the I/O pin is pulled low.
Enable the I
ON bit (I2CxCON<15>); but do not
configure the I2CxBRG register at this
time.
Execute a software delay loop of at
least 10 µs.
Set the TRIS bit of the I/O pin con-
nected to the SDAx pin. This will make
it an input pin, thereby ensuring that it
goes to a high logic state.
Execute a software delay loop of at
least 10 usec.
Configure the I2CxBRG register with
the value required by the application.
Issue a Start condition by setting the
SEN bit (I2CxCON<0>) as needed. I
communications can now proceed
normally.
2
C™
2
C bus transactions such as the
2
C module disabled, clear the
2
C node on the bus to
2
C module by setting the
2
C module to be
2
C bus:
2
C1 and
2
C
2. Module: Ethernet
3. Module: ADC
4. Module: Parallel Master Port
In 10 MB RMII mode only, pause frames are sent
at 10x the normal rate. This reduces the available
network bandwidth if the device is connected to
the network via a hub. This does not reduce
functionality or violate specifications.
Work around
If bandwidth is a concern, connect the PIC32
device to a network using an Ethernet switch.
Affected Silicon Revisions
The interrupt generated by the ADC module
cannot be cleared when the ADC module is
disabled.
Work around
Ensure the interrupt is serviced and the interrupt
flag is cleared before turning off the ADC module.
Affected Silicon Revisions
In Slave mode, a PMP interrupt will wake the
device; however, the interrupt source will not be
reflected in the interrupt flag until the end of the
write strobe.
Work around
There are two possible solutions to this issue:
1.
2.
Affected Silicon Revisions
A0
A0
A0
X
X
X
If multiple wake-up sources are to be used,
firmware can poll all of the configured wake-
up source interrupt flags. If none are set,
assume the source was the PMP.
Firmware can wait for a period exceeding
the write strobe length, and then poll the
PMP interrupt flag.
© 2010 Microchip Technology Inc.