PIC32MX795F512L-80I/BG Microchip Technology, PIC32MX795F512L-80I/BG Datasheet - Page 18
![IC, 32BIT MCU, PIC32, 80MHZ, BGA-100](/photos/12/13/121347/121-xbga_sml.jpg)
PIC32MX795F512L-80I/BG
Manufacturer Part Number
PIC32MX795F512L-80I/BG
Description
IC, 32BIT MCU, PIC32, 80MHZ, BGA-100
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.PIC32MX320F032H-40IPT.pdf
(66 pages)
2.PIC32MX575F256H-80IMR.pdf
(2 pages)
3.PIC32MX575F256H-80IMR.pdf
(254 pages)
4.PIC32MX575F256H-80IMR.pdf
(14 pages)
5.PIC32MX575F256H-80IPT.pdf
(240 pages)
Specifications of PIC32MX795F512L-80I/BG
Controller Family/series
PIC32
Ram Memory Size
128KB
Cpu Speed
80MHz
No. Of Timers
5
Interface
CAN, I2C, SPI, UART, USB
No. Of Pwm Channels
5
Core Size
32 Bit
Program Memory Size
512 KB
Core Processor
MIPS32® M4K™
Speed
80MHz
Connectivity
CAN, Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
121-TFBGA
Embedded Interface Type
CAN, I2C, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
PIC32MX7xx
Core
MIPS
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX795F512L-80I/BG
Manufacturer:
Microchip
Quantity:
316
Company:
Part Number:
PIC32MX795F512L-80I/BG
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC32MX
9.0
Before a device can be programmed, it must be
erased. The erase operation writes all ‘1s’ to the Flash
memory and prepares it to program a new set of data.
Once a device is erased, it can be verified by perform-
ing a “Blank Check” operation. See 9.1 “Blank Check”
for more information.
The procedure for erasing program memory (Program,
Boot, and Configuration memory) consists of selecting
the MTAP and sending the MCHP_ERASE command.
The programmer then must wait for the erase operation
to complete by reading and verifying bits in the
MCHP_STATUS value. Figure 9-1 illustrates the process
for performing a Chip Erase.
FIGURE 9-1:
DS61145G-page 18
Note:
ERASING THE DEVICE
The Device ID memory locations are read-
only and cannot be erased. Therefore,
Chip Erase has no effect on these memory
locations.
statusVal = XferData (MCHP_STATUS)
No
SendCommand (MTAP_SW_MTAP)
SendCommand (MTAP_COMMAND)
Put MTAP in Command Mode
Issue Chip Erase Command
XferData (MCHP_ERASE)
Read Erase Status
Select MTAP
ERASE DEVICE
CFGRDY = 1
FCBUSY = 0
Done
Yes
The following steps are required to erase a target
device:
1.
2.
3.
4.
5.
9.1
The term “Blank Check” implies verifying that the
device has been successfully erased and has no
programmed memory locations. A blank or erased
memory location always reads as ‘1’.
The device Configuration registers are ignored by the
Blank Check. Additionally, all unimplemented memory
space should be ignored from the Blank Check.
Note:
SendCommand (MTAP_SW_MTAP).
SendCommand (MTAP_COMMAND).
XferData (MCHP_ERASE).
statusVal = XferData (MCHP_STATUS).
If CFGRDY (statusVal<3>) is not ‘1’ and
FCBUSY (statusVal<4>) is not ‘0’, GOTO to
step 4.
Blank Check
The Chip Erase operation is a self-timed
operation. If the FCBUSY and CFGRDY
bits do not become properly set within the
specified Chip Erase time, the sequence
may have been executed wrong or the
device is damaged.
© 2010 Microchip Technology Inc.