LM5026MT National Semiconductor, LM5026MT Datasheet - Page 12

• Manufacturer Part Number: LM5026MT
• Description: IC, PWM ACTIVE CUR MODE, POWERWISE
• Manufacturer: National Semiconductor

Specifications of LM5026MT

• Input Voltage: 48V
• Output Current: 3A
• Frequency: 590kHz
• Supply Voltage Range: 8V To 15V
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +125°C
• Svhc: No SVHC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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For duty cycles greater than 50 percent, current mode control
circuits are subject to sub-harmonic oscillation. By adding an
additional fixed slope voltage ramp signal (slope compensa-
tion) to the current sense signal, this oscillation can be avoid-
ed. The LM5026 integrates this slope compensation by
summing a current ramp generated by the oscillator with the
current sense signal. The PWM comparator ramp signal is a
combination of the current waveform at the CS pin, and an
internally generated slope compensation ramp derived from
the oscillator. The internal ramp has an amplitude of 0 to 45
µA which is sourced into an internal 2 kΩ resistor, plus the
external impedance at the CS pin. Additional slope compen-
sation may be added by increasing the source impedance of
the current sense signal.
Maximum Duty Cycle Clamp
Controlling the maximum duty cycle of an active clamp reset
PWM controller is necessary to limit the voltage stress on the
main and active clamp MOSFETs. The relationship between
the maximum drain-source voltage of the MOSFETs and the
maximum PWM duty cycle is provided by the following equa-
tion:
The main output (OUT_A) duty cycle is normally controlled by
the control current sourced into the COMP pin from the ex-
ternal feedback circuit. When the feedback demands maxi-
mum output from the converter, the duty cycle will be limited
by one of two circuits within the LM5026: the user pro-
grammable duty cycle clamp and the voltage-dependent duty
cycle limiter, which varies inversely with the input line voltage.
Programmable Duty Cycle Clamp – The maximum allowed
duty cycle can be programmed by setting a voltage at the DCL
pin to a value less than 2V. The recommended method to set
the DCL pin voltage is with a resistor divider connected from
the RT pin to AGND. The voltage at the RT pin is internally
regulated to 2V, while the current sourced from the RT pin
sets the oscillator frequency. The maximum duty can be pro-
grammed, according to the following equation:
FIGURE 4. Opto-Coupler to LM5026 COMP Interface
12
Line Voltage Duty Cycle Limiter - The maximum duty cycle for
the main output driver is also limited by the voltage at the UV-
LO pin, which is normally proportional to VIN. The controller
outputs are disabled until the UVLO pin voltage exceeds
1.25V. At the minimum operating voltage (when UVLO =
1.25V) the maximum duty cycle starts at the duty cycle clamp
level programmed by the DCL pin voltage (80% or less). As
the line voltage increases, the maximum duty cycle decreas-
es linearly with increasing UVLO voltage, as illustrated in
Figure
trolled to the least of the following three variables: the duty
cycle controlled by the PWM comparator, the programmable
maximum duty cycle clamp, or the line voltage dependent
duty cycle limiter.
FIGURE 5. Programming oscillator Frequency and
6. Ultimately the duty cycle of the main output is con-
Maximum Duty Cycle Clamp
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