ADF7021BCPZ Analog Devices Inc, ADF7021BCPZ Datasheet
ADF7021BCPZ
Specifications of ADF7021BCPZ
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ADF7021BCPZ Summary of contents
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FEATURES Low power, narrow-band transceiver Frequency bands using dual VCO 80 MHz to 650 MHz 862 MHz to 950 MHz Modulation schemes 2FSK, 3FSK, 4FSK, MSK Spectral shaping Gaussian and raised cosine filtering Data rates supported 0.05 kbps to 32.8 ...
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ADF7021 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Specifications ..................................................................................... 5 RF and PLL Specifications ........................................................... 5 Transmission Specifications ........................................................ 6 Receiver Specifications ................................................................ 8 ...
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REVISION HISTORY 9/07—Rev Rev. A Change to UART/SPI Mode Section............................................. 14 Changes to Figure 10 ...................................................................... 16 Change to Table 8 ............................................................................ 16 Changes to Figure 12 ...................................................................... 18 Change to Internal Inductor VCO Section .................................. 24 Changes ...
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ADF7021 GENERAL DESCRIPTION The ADF7021 is a high performance, low power, highly integrated 2FSK/3FSK/4FSK transceiver designed to operate in the narrow-band, license-free ISM bands, and in the licensed bands with frequency ranges of 80 MHz to 650 MHz ...
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SPECIFICATIONS 3.6 V, GND = All measurements are performed with the EVAL-ADF7021DBx using the PN9 data sequence, unless otherwise noted. RF AND PLL SPECIFICATIONS Table 1. Parameter RF ...
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ADF7021 TRANSMISSION SPECIFICATIONS Table 2. Parameter DATA RATE 2FSK, 3FSK 4FSK MODULATION 3 Frequency Deviation (f ) DEV Deviation Frequency Resolution Gaussian Filter BT Raised Cosine Filter Alpha TRANSMIT POWER 4 Maximum Transmit Power Transmit Power Variation vs. Temperature Transmit ...
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Parameter SPURIOUS EMISSIONS Reference Spurs 5 HARMONICS Second Harmonic Third Harmonic All Other Harmonics 6 OPTIMUM PA LOAD IMPEDANCE f = 915 MHz 868 MHz 450 MHz 426 MHz RF f ...
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ADF7021 RECEIVER SPECIFICATIONS Table 3. Parameter Min SENSITIVITY 2FSK Sensitivity at 0.1 kbps Sensitivity at 0.25 kbps Sensitivity at 1 kbps Sensitivity at 9.6 kbps Sensitivity at 25 kbps Gaussian 2FSK Sensitivity at 0.1 kbps Sensitivity at 0.25 kbps Sensitivity ...
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Parameter Min ADJACENT CHANNEL REJECTION 868 MHz 12.5 kHz Channel Spacing 25 kHz Channel Spacing 25 kHz Channel Spacing 426 MHz, External Inductor VCO 12.5 kHz Channel Spacing 25 kHz Channel Spacing 25 kHz Channel Spacing CO-CHANNEL REJECTION 868 MHz ...
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ADF7021 Parameter Min LNA INPUT IMPEDANCE f = 915 MHz 868 MHz 450 MHz 426 MHz 315 MHz 175 MHz RF 1 Calibration of the ...
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GENERAL SPECIFICATIONS Table 5. Parameter TEMPERATURE RANGE ( POWER SUPPLIES Voltage Supply TRANSMIT CURRENT CONSUMPTION 868 MHz 0 dBm 5 dBm 10 dBm 450 MHz, Internal Inductor VCO 0 dBm 5 dBm 10 dBm 426 ...
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ADF7021 Timing Diagrams Serial Interface SCLK DATA DB31 (MSB) SLE SCLK SDATA REG7 DB0 (CONTROL BIT C1) SLE t 3 SREAD t 8 2FSK/3FSK Timing ±1 × DATA RATE/32 TxRxCLK TxRxDATA TxRxCLK TxRxDATA ...
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Timing In 4FSK receive mode, MSB/LSB synchronization should be guaranteed by SWD in the receive bit stream. t SYMBOL t BIT SLE TxRxCLK Rx SYMBOL TxRxDATA MSB Tx/Rx MODE SLE TxRxCLK Tx SYMBOL TxRxDATA MSB Tx/Rx MODE REGISTER 0 ...
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ADF7021 UART/SPI Mode UART mode is enabled by setting R0_DB28 to 1. SPI mode is enabled by setting R0_DB28 to 1 and setting R15_DB[17:19] to 0x7. The transmit/receive data clock is available on the CLKOUT pin. CLKOUT (TRANSMIT/RECEIVE DATA CLOCK ...
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ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 7. Parameter GND DD Analog I/O Voltage to GND Digital I/O Voltage to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature ...
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ADF7021 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 8. Pin Function Descriptions Pin No. Mnemonic Description 1 VCOIN The tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (VCO). The higher the tuning voltage, the higher ...
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Pin No. Mnemonic Description 29 GND2 Ground for Digital Section. 30 ADCIN Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale 1.9 V. Readback is made using the SREAD pin. ...
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ADF7021 TYPICAL PERFORMANCE CHARACTERISTICS –70 –80 = 0.8mA – –100 –110 I = 2.2mA –120 CP –130 –140 –150 1 10 100 FREQUENCY OFFSET (MHz) Figure 11. Phase Noise Response at 900 MHz ...
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REF 15dBm ATTEN 25dB SAMP LOG 10dB 9.6kbps DATA = PRS9 f RF FREQ = 869.5MHz VAVG 100 3FSK RC3FSK CENTER 869.5MHz VBW 300Hz RES BW 300Hz Figure 17. Output Spectrum in 3FSK and ...
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ADF7021 FREQ = 868MHz 40 WANTED SIGNAL (10dB ABOVE SENSITIVITY 30 POINT) = 2FSK, f DEV 20 DATA RATE = 9.8kbps BLOCKER = 2FSK DEV DATA RATE = 9.8kbps ...
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RF I/P LEVEL = –70dBm 12.5kHz DATA RATE = 10kbps POST DEMOD BW = 12.4kHz f = 2.5kHz DEV 4 20834 ACQS M 20µs Figure 29. 3FSK Receiver Eye Diagram Measured Using the Test ...
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ADF7021 FREQUENCY SYNTHESIZER REFERENCE INPUT The on-board crystal oscillator circuitry (see Figure 31) can use a quartz crystal as the PLL reference. Using a quartz crystal with a frequency tolerance of ≤10 ppm for narrow-band appli- cations is recommended. It ...
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The free design tool ADIsimPLL can also be used to design loop filters for the ADF7021 (go to www.analog.com/ADIsimPLL details). N Counter The feedback divider in the ADF7021 PLL consists of an 8-bit integer counter (R0_DB[19:26]) and a 15-bit Σ-Δ ...
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ADF7021 VOLTAGE CONTROLLED OSCILLATOR (VCO) The ADF7021 contains two VCO cores. The first VCO, the internal inductor VCO, uses an internal LC tank and supports 862 MHz to 950 MHz and 431 MHz to 475 MHz operating bands. The second ...
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CHOOSING CHANNELS FOR BEST SYSTEM PERFORMANCE An interaction between the RF VCO frequency and the reference frequency can lead to fractional spur creation. When the synthesizer is in fractional mode (that is, the RF VCO and reference frequencies are not ...
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ADF7021 TRANSMITTER RF OUTPUT STAGE The power amplifier (PA) of the ADF7021 is based on a single- ended, controlled current, open-drain amplifier that has been designed to deliver dBm into a 50 Ω load at a maximum ...
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Setting the Transmit Data Rate In all modulation modes except oversampled 2FSK mode, an accurate clock is provided on the TxRxCLK pin to latch the data from the microcontroller into the transmit section at the required data rate. The exact ...
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ADF7021 Table 10. 3-Level Signal Mapping of the Convolutional Encoder TxDATA Precoder Output Encoder Output +1 0 −1 +1 Another property of this encoding scheme is that the transmitted symbol sequence is ...
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MODULATION AND FILTERING OPTIONS The various modulation and data filtering options are described in Table 11. Table 11. Modulation and Filtering Options Modulation Data Filtering BINARY FSK 2FSK None 1 MSK None OQPSK with half sine None 2 baseband shaping ...
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ADF7021 RECEIVER SECTION RF FRONT END The ADF7021 is based on a fully integrated, low IF receiver architecture. The low IF architecture facilitates a very low external component count and does not suffer from powerline- induced interference problems. Figure 44 ...
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The calibration algorithm adjusts the filter center frequency and measures the RSSI 10 times during the calibration. The time for an adjustment plus RSSI measurement is given by IF_CAL_DWE = IF Tone Calibratio n Time It is recommended that the ...
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ADF7021 RSSI Formula (Converting to dBm) The RSSI formula is Input Power [dBm] = −130 dBm + (Readback Code + Gain Mode Correction) × 0.5 where: Readback Code is given by Bit RV7 to Bit RV1 in the readback register ...
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Linear Demodulator Figure 48 shows a block diagram of the linear demodulator. I LEVEL IF LIMITER Q FREQUENCY LINEAR DISCRIMINATOR R4_DB(20:29) Figure 48. Block Diagram of Linear FSK Demodulator A digital frequency discriminator provides an output signal that is linearly ...
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ADF7021 example, using 2FSK with Manchester-encoded data achieves a data rate tolerance of ±2.0%. The CDR PLL is designed for fast acquisition of the recovered symbols during preamble and typically achieves bit synchro- nization within 5-symbol transitions of preamble. In ...
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Viterbi Detector Setup The Viterbi detector can be used for 3FSK data detection. This is activated by setting R13_DB11 to Logic 1. The Viterbi path memory length is programmable in steps bits (VITERBI_PATH_MEMORY, ...
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ADF7021 DEMODULATOR CONSIDERATIONS 2FSK Preamble The recommended preamble bit pattern for 2FSK is a dc-free pattern (such as a 10101010… pattern). Preamble patterns with longer run-length constraints (such as 11001100…) can also be used but result in a longer synchronization ...
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Maximum AFC Range The maximum frequency correction range of the AFC loop is programmable on the ADF7021. This is set by R10_DB[24:31]. The maximum AFC correction range is the difference in frequency between the upper and lower limits of the ...
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ADF7021 APPLICATIONS INFORMATION IF FILTER BANDWIDTH CALIBRATION The IF filter should be calibrated on every power-up in receive mode to correct for errors in the bandwidth and filter center frequency due to process variations. The automatic calibration requires no external ...
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V BAT L1 C1 ANTENNA Z _PA OPTIONAL OPT BPF OR LPF Z _RFIN _RFIN Figure 49. ADF7021 with Internal Rx/Tx Switch The procedure typically requires several iterations until an acceptable ...
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ADF7021 RFIN LNA RFINB INTERNAL Figure 51. Image Rejection Calibration Using the Internal Calibration Source and a Microcontroller Using the internal RF source, the RF frequencies that can be utilized for image calibration are programmable and are odd multiples of ...
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PACKET STRUCTURE AND CODING The suggested packet structure to use with the ADF7021 is shown in Figure 53. SYNC ID PREAMBLE WORD FIELD DATA FIELD Figure 53. Typical Format of a Transmit Protocol Refer to the Receiver Setup section for ...
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ADF7021 CE HIGH WAIT 10µs (REGULATOR POWER-UP) OPTIONAL. ONLY NECESSARY IF PA RAMP DOWN IS REQUIRED. TCXO REFERENCE POWER-DOWN CE LOW WRITE TO REGISTER 1 (TURNS ON VCO) WAIT 0.7ms (TYPICAL VCO SETTLING) WRITE TO REGISTER 3 (TURNS ON Tx/Rx ...
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TCXO REFERENCE CE HIGH WAIT 10µs (REGULATOR POWER-UP) WRITE TO REGISTER 1 (TURNS ON VCO) WAIT 0.7ms (TYPICAL VCO SETTLING) WRITE TO REGISTER 3 WRITE TO REGISTER 6 (SETS UP IF FILTER CALIBRATION) WRITE TO REGISTER 5 (STARTS IF FILTER ...
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ADF7021 APPLICATONS CIRCUIT The ADF7021 requires very few external components for operation. Figure 56 shows the recommended application circuit. Note that the power supply decoupling and regulator capacitors are omitted for clarity. MATCHING T-STAGE LC ANTENNA FILTER CONNECTION RESISTOR *PIN ...
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SERIAL INTERFACE The serial interface allows the user to program the 16-/32-bit registers using a 3-wire interface (SCLK, SDATA, and SLE). It consists of a level shifter, 32-bit shift register, and 16 latches. Signals should be CMOS compatible. The serial ...
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ADF7021 INTERFACING TO MICROCONTROLLER/DSP Standard Transmit/Receive Data Interface The standard transmit/receive signal and configuration interface to a microcontroller is shown in Figure 58. In transmit mode, the ADF7021 provides the data clock on the TxRxCLK pin, and the TxRxDATA pin ...
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REGISTER 0—N REGISTER MUXOUT 8-BIT INTEGER_N TRANSMIT/ TR1 RECEIVE 0 TRANSMIT 1 RECEIVE U1 UART MODE 0 DISABLED 1 ENABLED MUXOUT REGULATOR_READY (DEFAULT FILTER_CAL_COMPLETE DIGITAL_LOCK_DETECT ...
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ADF7021 REGISTER 1—VCO/OSCILLATOR REGISTER VCO CENTER VA2 VA1 FREQ ADJUST 0 0 NOMINAL 0 1 VCO ADJUST VCO ADJUST VCO ADJUST UP 3 VB4 VB3 VB2 VB1 ...
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REGISTER 2—TRANSMIT MODULATION REGISTER TxDATA_ INVERT Tx_FREQUENCY_DEVIATION DI2 DI1 TxDATA INVERT 0 0 NORMAL 0 1 INVERT CLK 1 0 INVERT DATA 1 1 INV CLK AND DATA TFD9 ... TFD3 TFD2 0 ... 0 0 ... ...
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ADF7021 REGISTER 3—TRANSMIT/RECEIVE CLOCK REGISTER AGC_CLK_DIVIDE SEQUENCER_CLK_DIVIDE GD6 GD5 GD4 GD3 GD2 GD1 ... ... ... ... ... ... Baseband offset clock ...
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REGISTER 4—DEMODULATOR SETUP REGISTER IF_BW POST_DEMOD_BW IF FILTER IFB2 IFB1 12.5kHz 0 1 18.75kHz 1 0 25kHz 1 1 INVALID POST DEMOD DW10 . DW6 DW5 DW4 DW2 DW3 DW1 ...
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ADF7021 REGISTER 5—IF FILTER SETUP REGISTER IR_GAIN_ ADJUST_MAG PD1 IR PHASE ADJUST I/Q 0 ADJUST ADJUST Q CH GM5 GM4 GM3 GM2 GM1 ...
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REGISTER 6—IF FINE CAL SETUP REGISTER IF_CAL_DWELL_TIME IRD1 IR CAL SOURCE ÷2 0 SOURCE ÷2 OFF 1 SOURCE ÷ CAL SOURCE IRC2 IRC1 DRIVE LEVEL 0 0 OFF 0 1 LOW 1 0 MED 1 1 HIGH CD3 ...
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ADF7021 REGISTER 7—READBACK SETUP REGISTER RB3 READBACK 0 DISABLED 1 ENABLED Readback of the measured RSSI value is valid only in Rx mode. Readback of the battery voltage, temperature sensor, or voltage at the external pin is not valid in ...
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REGISTER 8—POWER-DOWN TEST REGISTER Rx_RESET DB15 DB14 CR1 CR1 COUNTER RESET 0 NORMAL 1 RESET CDR RESET PD7 PA (Rx MODE OFF SW1 0 1 LE1 LOG AMP ENABLE 0 LOG AMP OFF 1 LOG ...
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ADF7021 REGISTER 9—AGC REGISTER ML1 MIXER LINEARITY 0 DEFAULT 1 HIGH LI2 LI1 LNA BIAS 0 0 800µA (DEFAULT) LG1 LNA MODE 0 DEFAULT 1 REDUCED GAIN FI1 FILTER CURRENT 0 LOW 1 HIGH FG2 FG1 FILTER GAIN 0 0 ...
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REGISTER 10—AFC REGISTER MAX_AFC_RANGE KP3 KP2 KP1 MAX AFC ... MA3 MA2 MA1 MA8 RANGE 0 ... ... ...
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ADF7021 REGISTER 11—SYNC WORD DETECT REGISTER REGISTER 12—SWD/THRESHOLD SETUP REGISTER SWD MODE 0 SWD PIN LOW 1 SWD PIN HIGH AFTER NEXT SYNCWORD 2 SWD PIN HIGH AFTER NEXT SYNCWORD FOR DATA PACKET LENGTH NUMBER OF BYTES 3 INTERRUPT PIN ...
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REGISTER 13—3FSK/4FSK DEMOD REGISTER Refer to the Receiver Setup section for information about programming these settings. 3FSK_PREAMBLE_ TIME_VALIDATE 3FSK_CDR_THRESHOLD VT7 ... VT3 0 ... 0 0 ... 0 0 ... 0 0 ... ... . . ... ...
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ADF7021 REGISTER 14—TEST DAC REGISTER TEST_DAC_GAIN ED LEAK FACTOR ED PEAK RESPONSE LEAKAGE = 0 FULL RESPONSE TO PEAK 0 2^–8 1 0.5 RESPONSE TO PEAK 1 2^–9 2 0.25 RESPONSE TO PEAK 2 2^–10 3 0.125 RESPONSE TO PEAK ...
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REGISTER 15—TEST MODE REGISTER ANALOG_TEST_ MODES CAL OVERRIDE 0 AUTO CAL 1 OVERRIDE GAIN 2 OVERRIDE BW 3 OVERRIDE BW AND GAIN REG1 PD 0 NORMAL 1 PWR DWN FORCE LD HIGH 0 NORMAL 1 FORCE ANALOG TEST MODES 0 ...
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... INDICATOR 1.00 12° MAX 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range 1 ADF7021BCPZ −40°C to +85°C 1 ADF7021BCPZ-RL −40°C to +85°C 1 ADF7021BCPZ-RL7 −40°C to +85°C EVAL-ADF70XXMBZ 1 1 EVAL-ADF70XXMBZ2 1 EVAL-ADF7021DBJZ 1 EVAL-ADF7021DBZ2 1 EVAL-ADF7021DBZ3 RoHS Compliant Part. 7.00 BSC SQ 0.60 MAX ...
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NOTES Rev Page ADF7021 ...
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ADF7021 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05876-0-9/07(A) Rev Page ...