AD669BR Analog Devices Inc, AD669BR Datasheet - Page 8

• Manufacturer Part Number: AD669BR
• Description: IC,D/A CONVERTER,SINGLE,16-BIT,BICMOS,SOP,28PIN
• Manufacturer: Analog Devices Inc
• Series: DACPORT®r

Specifications of AD669BR

• Rohs Compliant: NO
• Rohs Status: RoHS non-compliant
• Settling Time: 10µs
• Number Of Bits: 16
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 625mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Converter Type: DAC
• Current, Output: 5 mA (Min.)
• Number Of Pins: 28
• Package Type: SOIC
• Power Dissipation: 365 mW (Typ.)
• Resolution: 16 Bits (Min.)
• Temperature, Operating, Maximum: 85 °C
• Temperature, Operating, Minimum: -40 °C
• Voltage, Input, High Level: 2 V (Min.)
• Voltage, Input, Low Level: 0 to 0.8 V
• Voltage, Output: 0 to +10 V (Unipolar), -10 to +10 V (Bipolar)
• Voltage, Range: +13.5 to +16.5 V
• Resolution (bits): 16bit
• Sampling Rate: 167kSPS
• Input Channel Type: Parallel
• Supply Voltage Range - Analog: 13.5V To 16.5V
• Supply Current: 12mA
• Digital Ic Case Style: SOIC

AD669
OUTPUT SETTLING AND GLITCH
The AD669’s output buffer amplifier typically settles to within
0.0008% FS (l/2 LSB) of its final value in 8 s for a full-scale
step. Figures 7a and 7b show settling for a full-scale and an LSB
step, respectively, with a 2 k , 1000 pF load applied. The guar-
anteed maximum settling time at +25 C for a full-scale step is
13 s with this load. The typical settling time for a 1 LSB step is
2.5 s.
The digital-to-analog glitch impulse is specified as 15 nV-s typi-
cal. Figure 7c shows the typical glitch impulse characteristic at
the code 011 . . . 111 to 100 . . . 000 transition when loading
the second rank register from the first rank register.
+10
–10
a. –10 V to +10 V Full-Scale Step Settling
–200
–400
–600
0
+10
–10
600
400
200
0
0
0
0
0
Figure 7. Output Characteristics
c. D-to-A Glitch Impulse
b. LSB Step Settling
1
1
2
2
10
s
s
s
3
3
4
4
20
5
5
600
400
200
0
–200
–400
–600
–8–
DIGITAL CIRCUIT DETAILS
The bus interface logic of the AD669 consists of two indepen-
dently addressable registers in two ranks. The first rank consists
of a 16-bit register which is loaded directly from a 16-bit micro-
processor bus. Once the 16-bit data word has been loaded in the
first rank, it can be loaded into the 16-bit register of the second
rank. This double-buffered organization avoids the generation of
spurious analog output values.
The first rank latch is controlled by CS and L1. Both of these
inputs are active low and are level-triggered. This means that
data present during the time when both CS and L1 are low will
enter the latch. When either one of these signals returns high,
the data is latched.
The second rank latch is controlled by LDAC. This input is ac-
tive high and is also level-triggered. Data that is present when
LDAC is high will enter the latch, and hence the DAC will
change state. When this pin returns low, the data is latched in
the DAC.
Note that LDAC is not gated with CS or any other control sig-
nal. This makes it possible to simultaneously update all of the
AD669’s present in a multi-DAC system by tying the LDAC
pins together. After the first rank register of each DAC has been
individually loaded and latched, the second rank registers are
then brought high together, updating all of the DACs at the
same time. To reduce bit skew, it is suggested to leave 100 ns
between the first rank load and the second rank load.
The first rank latch and second rank latch can be used together
in a master-slave or edge-triggered configuration. This mode of
operation occurs when LDAC and CS are tied together with L1
tied to ground. Rising edges on the LDAC-CS pair will update
the DAC with the data presented preceding the edge. The tim-
ing diagram for operation in this mode can be seen in Figure lb.
Note, however, that the sum of t
enough to allow the DAC output to settle to its new value.
“X” = Don’t Care
It is possible to make the second rank register transparent by ty-
ing Pin 23 high. Any data appearing in the first rank register will
then appear at the output of the DAC. It should be noted, how-
ever, that the deskewing provided by the second rank latch is
then defeated, and glitch impulse may increase. If it is desired to
make both registers transparent, this can be done by tying Pins
5 and 6 low and Pin 23 high. Table I shows the truth table for
the AD669, while the timing diagram is found in Figure 1.
INPUT CODING
The AD669 uses positive-true binary input coding. Logic “1” is
represented by an input voltage greater than 2.0 V, and Logic
“0” is defined as an input voltage less than 0.8 V.
CS
0
X
1
X
X
0
L1
0
1
X
X
X
0
Table I. AD669 Truth Table
LDAC
X
X
X
1
0
1
LOW
Operation
First Rank Enable
First Rank Latched
First Rank Latched
Second Rank Enabled
Second Rank Latched
All Latches Transparent
and t
HIGH
must be long
REV. A