AD9764ARZ Analog Devices Inc, AD9764ARZ Datasheet - Page 6

• Manufacturer Part Number: AD9764ARZ
• Description: IC,D/A CONVERTER,SINGLE,14-BIT,CMOS,SOP,28PIN
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9764ARZ

• Rohs Compliant: YES
• Settling Time: 35ns
• Number Of Bits: 14
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 170mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9764-EB - BOARD EVAL FOR AD9764
• Data Interface: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9764
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input
code.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For I
inputs are all 0s. For I
inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (+25 C) value to the value at either T
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is
reported in ppm per degree C.
DCOM
DVDD
RETIMED
OUTPUT*
CLOCK
PULSE GENERATOR
R
LECROY 9210
2k
SET
OUTB
OUTA
50
0.1 F
+5V
, 0 mA output is expected when all
, 0 mA output is expected when the
CLOCK
REFIO
FS ADJ
DVDD
DCOM
SLEEP
+1.20V REF
OUTPUT
CLOCK
REFLO
Figure 2. Basic AC Characterization Test Setup
SEGMENTED SWITCHES
FOR DB13–DB5
MIN
or T
50pF
TEKTRONIX
MAX
AWG-2021
COMP1
LATCHES
DIGITAL
DATA
CURRENT SOURCE
0.1 F
. For
ARRAY
PMOS
+5V
–6–
SWITCHES
AVDD
LSB
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied over a specified range.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion
THD is the ratio of the sum of the rms value of the first six
harmonic components to the rms value of the measured output
signal. It is expressed as a percentage or in decibels (dB).
Multitone Power Ratio
The spurious-free dynamic range for an output containing mul-
tiple carrier tones of equal amplitude. It is measured as the
difference between the rms amplitude of a carrier tone to the
peak spurious signal in the region of a removed tone.
AD9764
ACOM
COMP2
I
I
OUTB
OUTA
50
0.1 F
20pF
50
* AWG2021 CLOCK RETIMED
SUCH THAT DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.
20pF
100
MINI-CIRCUITS
T1-1T
TO HP3589A
SPECTRUM/
NETWORK
ANALYZER
50
INPUT
REV. B