PIC16C926-I/L Microchip Technology, PIC16C926-I/L Datasheet
PIC16C926-I/L
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PIC16C926-I/L Summary of contents
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... CMOS Microcontrollers 2001 Microchip Technology Inc. PIC16C925/926 Data Sheet with LCD Driver Preliminary DS39544A ...
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... Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. No licenses are conveyed, implicitly or otherwise, under any intellectual prop- erty rights.” ...
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... Segment 2001 Microchip Technology Inc. PIC16C925/926 Analog Features: • 10-bit 5-channel Analog-to-Digital Converter (A/D) • Brown-out Reset (BOR) Special Microcontroller Features: • Power-on Reset (POR) • Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation • ...
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... OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI LEGEND: Input Pin Output Pin Input/Output Pin Digital Input/LCD Output Pin LCD Output Pin DS39544A-page PIC16C92X Preliminary 60 RD5/SEG29/COM3 59 RG6/SEG26 58 RG5/SEG25 57 RG4/SEG24 56 RG3/SEG23 55 RG2/SEG22 54 RG1/SEG21 53 RG0/SEG20 52 RG7/SEG28 51 RF7/SEG19 50 RF6/SEG18 49 RF5/SEG17 48 RF4/SEG16 47 RF3/SEG15 46 RF2/SEG14 45 RF1/SEG13 44 RF0/SEG12 2001 Microchip Technology Inc. ...
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... Pin Diagrams (Continued) TQFP RA4/T0CKI RA5/AN4/SS RB1 RB0/INT RC3/SCK/SCL RC4/SDI/SDA RC5/SDO LCD V 3 LCD OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI LEGEND: Input Pin Output Pin Input/Output Pin Digital Input/LCD Output Pin LCD Output Pin 2001 Microchip Technology Inc PIC16C92X Preliminary PIC16C925/926 48 RD5/SEG29/COM3 47 RG6/SEG26 46 RG5/SEG25 45 RG4/SEG24 44 RG3/SEG23 ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter- ature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. DS39544A-page 4 Preliminary 2001 Microchip Technology Inc. ...
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... An overview of features is presented in Table 1-1. A UV-erasable, CERQUAD packaged version (compat- ible with PLCC) is also available for both the PIC16C925 and PIC16C926. This version is ideal for cost effective code development. A block diagram for the PIC16C925/926 family archi- tecture is presented in Figure 1-1. ...
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... Preliminary PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/V REF RA4/T0CKI RA5/AN4/SS PORTB RB0/INT RB1-RB7 PORTC RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO PORTD RD0-RD4/SEGnn RD5-RD7/SEGnn/COMn PORTE RE0-RE7/SEGnn PORTF RF0-RF7/SEGnn PORTG RG0-RG7/SEGnn COM0 V 1 LCD V 2 LCD V 3 LCD C1 C2 VLCDADJ 2001 Microchip Technology Inc. ...
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... COM0 63 51 Legend input O = output — = Not used TTL = TTL input 2001 Microchip Technology Inc. PIC16C925/926 Pin Buffer Type Type I ST/CMOS Oscillator crystal input or external clock source input. This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. ...
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... Analog Power (PLCC and CLCC packages only). P — LCD Voltage. P — LCD Voltage. P — LCD Voltage. P — Digital power. P — Ground reference. — — These pins are not internally connected. These pins should be left unconnected power L = LCD Driver ST = Schmitt Trigger input Preliminary Description 2001 Microchip Technology Inc. ...
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... Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. 2001 Microchip Technology Inc. PIC16C925/926 1.2 Instruction Flow/Pipelining An “ ...
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... PIC16C925/926 NOTES: DS39544A-page 10 Preliminary 2001 Microchip Technology Inc. ...
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... On-chip Program 0FFFh Memory 1000h 1FFFh 2000h 2003h 2004h 2007h 3FFFh Preliminary PROGRAM MEMORY MAP AND STACK FOR PIC16C926 PC<12:0> 13 Stack Level 1 Stack Level 2 Stack Level 8 RESET Vector 0000h Interrupt Vector 0004h 0005h Page 0 07FFh 0800h Page 1 0FFFh 1000h ...
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... File (Section 2.6). The following General Purpose Registers are not phys- ically implemented: • F0h-FFh of Bank 1 • 170h-17Fh of Bank 2 • 1F0h-1FFh of Bank 3 These locations are used for common access across banks. Preliminary Select Register FSR 2001 Microchip Technology Inc. ...
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... ADCON1 20h Purpose Register General Purpose Register accesses 70h - 7Fh 7Fh Bank 0 Unimplemented data memory locations, read as ’0’. * Not a physical register. 2001 Microchip Technology Inc. File Address Indirect addr.(*) 80h TMR0 OPTION 81h PCL PCL 82h STATUS STATUS 83h ...
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... PIC16C925/926 FIGURE 2-4: REGISTER FILE MAP— PIC16C926 File Address Indirect addr.(*) Indirect addr.(*) 00h TMR0 01h 02h PCL STATUS 03h FSR 04h PORTA 05h 06h PORTB PORTC 07h PORTD 08h 09h PORTE PCLATH 0Ah INTCON 0Bh 0Ch PIR1 0Dh TMR1L ...
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... Shaded locations are unimplemented, read as ‘0’. Note 1: These pixels do not display, but can be used as general purpose RAM. 2001 Microchip Technology Inc. The special function registers can be classified into two sets, core and peripheral. Those registers associated with the “ ...
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... 0000 0000 — — — — — — — — — — — — — — — — — — 79 xxxx xxxx PCFG1 PCFG0 76 ---- -000 2001 Microchip Technology Inc. ...
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... SEG30 (1) (1) COM3 COM3 Legend unknown unchanged value depends on condition unimplemented, read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: These pixels do not display, but can be used as general purpose RAM. 2001 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 RP0 — ...
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... Microchip Technology Inc. ...
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... Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged recommended, therefore, that only BCF, BSF, ...
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... TMR0 register, assign the prescaler to the Watchdog Timer. R/W-1 R/W-1 R/W-1 R/W-1 T0CS T0SE PSA PS2 128 W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Preliminary R/W-1 R/W-1 PS1 PS0 bit Bit is unknown 2001 Microchip Technology Inc. ...
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... At least one of the RB7:RB4 pins changed state (must be cleared in software None of the RB7:RB4 pins have changed state Legend Readable bit - n = Value at POR reset 2001 Microchip Technology Inc. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON< ...
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... Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. U-0 U-0 R/W-0 R/W-0 — — SSPIE CCP1IE W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Preliminary R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown 2001 Microchip Technology Inc. ...
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... TMR1 register overflowed (must be cleared in software TMR1 register did not overflow Legend Readable bit - n = Value at POR reset 2001 Microchip Technology Inc. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User soft- ...
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... Value at POR DS39544A-page 24 U-0 U-0 U-0 U-0 — — — — Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Preliminary U-0 R/W-0 R/W-1 — POR BOR bit Bit is unknown 2001 Microchip Technology Inc. ...
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... PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). 2001 Microchip Technology Inc. PIC16C925/926 Note 1: There are no status bits to indicate stack overflow or stack underflow conditions. ...
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... GOTO CONTINUE : 0 IRP Bank Select 00h Bank 1 Bank 2 Bank 3 Preliminary INDIRECT ADDRESSING ;initialize pointer ;to RAM INDF ;clear INDF register FSR,F ;inc pointer ;all done? NEXT ;no clear next ;yes continue Indirect Addressing 7 0 FSR Register Location Select 7Fh 2001 Microchip Technology Inc. ...
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... Initiates a read cleared in hardware. The RD bit can only be set (not cleared) in software Does not initiate a read Legend Readable bit - n = Value at POR reset 2001 Microchip Technology Inc. PIC16C925/926 When interfacing to the program memory block, the PMDATH:PMDATA registers form a two-byte word, which holds ...
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... Data Register High Byte — Address Register High Byte Preliminary Value on Value on: Bit 0 all other POR, BOR RESETS RD 1--- ---0 1--- ---0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 2001 Microchip Technology Inc. ...
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... STATUS, RP0 ; Select Bank1 MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs ; RA<7:6> are always ; read as ’0’. 2001 Microchip Technology Inc. PIC16C925/926 FIGURE 4-1: BLOCK DIAGRAM OF PINS RA3:RA0 AND RA5 Data Bus Port CK Q Data Latch ...
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... Input/output or analog input or slave select input for synchronous serial port. Bit 4 Bit 3 Bit 2 Bit 1 RA4 RA3 RA2 RA1 — — — PCFG2 PCFG1 Preliminary Value on Value on Bit 0 Power-on all other Reset RESETS RA0 --0x 0000 --0x 0000 --11 1111 --11 1111 PCFG0 ---- -000 ---- -000 2001 Microchip Technology Inc. ...
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... I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION<7>). 2001 Microchip Technology Inc. Four of the PORTB pins (RB7:RB4) have an interrupt-on-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupt-on-change comparison) ...
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... Bit 4 Bit 3 Bit 2 Bit 1 RB5 RB4 RB3 RB2 RB1 T0CS T0SE PSA PS2 PS1 Preliminary Value on Value on all Bit 0 Power-on other Reset RESETS RB0 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 PS0 1111 1111 1111 1111 2001 Microchip Technology Inc. ...
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... Name Bit 7 Bit 6 07h PORTC — — 87h TRISC — — Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by PORTC. 2001 Microchip Technology Inc. FIGURE 4-5: (2) RBPU Data Bus WR Port read- WR TRIS RD TRIS RD Port RB0/INT Note 1: I/O pins have diode protection to V ...
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... Segment Data LCD Segment Output Enable LCD Common Data LCD Common Output Enable LCDSE<n> Data Bus RD Port RD TRIS I/O pin Schmitt Trigger Input Buffer Preliminary PORTD<7:5> BLOCK DIAGRAM Digital Input/ LCD Output pin Schmitt Trigger Input Buffer 2001 Microchip Technology Inc. ...
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... TRISD PORTD Data Direction Control Register 10Dh LCDSE SE29 SE27 Legend: Shaded cells are not used by PORTD. 2001 Microchip Technology Inc. ST Input/output port pin or Segment Driver00. ST Input/output port pin or Segment Driver01. ST Input/output port pin or Segment Driver02. ST Input/output port pin or Segment Driver03. ...
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... SE20 SE16 SE12 SE9 SE5 Preliminary Digital Input/ LCD Output pin Schmitt Trigger Input Buffer Value on Value on all Bit 0 Power-on other Reset RESETS RE0 0000 0000 0000 0000 1111 1111 1111 1111 SE0 1111 1111 1111 1111 2001 Microchip Technology Inc. ...
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... RF7 RF6 187h TRISF PORTF Data Direction Control Register 10Dh LCDSE SE29 SE27 Legend: Shaded cells are not used by PORTF. 2001 Microchip Technology Inc. FIGURE 4-8: LCD Segment Data LCD Segment Output Enable LCD Common Data LCD Common Output Enable LCDSE<n> ...
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... SE9 SE5 Preliminary PORTG BLOCK DIAGRAM Digital Input/ LCD Output pin Schmitt Trigger Input Buffer Value on Value on all Bit 0 Power-on other Reset RESETS RG0 0000 0000 0000 0000 1111 1111 1111 1111 SE0 1111 1111 1111 1111 2001 Microchip Technology Inc. ...
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... MOVWF PORTB MOVF PORTB,W Instruction write to Fetched PORTB RB7:RB0 Instruction MOVWF PORTB Executed write to PORTB 2001 Microchip Technology Inc. PIC16C925/926 EXAMPLE 4-8: ;Initial PORT settings: PORTB<7:4> Inputs ; ;PORTB<7:6> have external pull-ups and are ;not connected to other circuitry ; ; ; BCF PORTB, 7 BCF PORTB, 6 BCF STATUS, RP1 ...
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... PIC16C925/926 NOTES: DS39544A-page 40 Preliminary 2001 Microchip Technology Inc. ...
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... T0SE T0CS Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION<5:0>). 2: The prescaler is shared with the Watchdog Timer (refer to Figure 5-6 for detailed block diagram). 2001 Microchip Technology Inc. PIC16C925/926 bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 5 ...
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... Read TMR0 Read TMR0 Read TMR0 reads NT0 reads NT0 + 1 reads NT0 + 2 PC+4 PC+5 PC+6 NT0+1 PC+6 Read TMR0 Read TMR0 reads NT0 reads NT0 + 01h 02h 0004h 0005h Inst (0004h) Inst (0005h) Dummy cycle Inst (0004h) 2001 Microchip Technology Inc. T0 ...
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... Timer0 input = 4T 2: External clock if no prescaler selected, prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs. 2001 Microchip Technology Inc. PIC16C925/926 When a prescaler is used, the external clock input is divided by the asynchronous ripple counter type pres- caler, so that the prescaler output is symmetrical ...
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... Writing to TMR0 when the prescaler is assigned to Timer0, will clear the prescaler count, but will not change the prescaler assignment SYNC Cycles X T0CS PSA 8-bit Prescaler MUX PS2:PS0 PSA WDT Time-out Preliminary Data Bus 8 TMR0 reg Set Flag bit TMR0IF on Overflow 2001 Microchip Technology Inc. ...
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... TRISA — — Legend unknown unchanged unimplemented locations read as '0'. Shaded cells are not used by Timer0. 2001 Microchip Technology Inc. Note: To avoid an unintended device RESET, the following instruction sequence (shown in Example 5-1) must be executed when changing the prescaler assignment from Timer0 to the WDT ...
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... PIC16C925/926 NOTES: DS39544A-page 46 Preliminary 2001 Microchip Technology Inc. ...
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... TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. In Timer mode, Timer1 increments every instruction cycle. In Counter mode, it increments on every rising edge of the external clock input. Timer1 can be turned on and off using the control bit Register pair TMR1ON (T1CON< ...
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... TMR1 TMR1L TMR1ON T1SYNC On/Off 1 Prescaler T1OSCEN F /4 OSC Enable Internal 0 (1) Oscillator Clock T1CKPS1:T1CKPS0 TMR1CS Preliminary ) synchronization. Also, OSC (and OSC OSC (and a small RC delay OSC Synchronized 0 Clock Input 1 Synchronize det 2 SLEEP Input 2001 Microchip Technology Inc. ...
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... MOVWF TMPL ; ; Re-enable the Interrupt (if required) ; CONTINUE ;Continue with your code 2001 Microchip Technology Inc. PIC16C925/926 6.3.2 READING AND WRITING TMR1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L, while the timer is running from an external asynchronous clock, will ensure a valid read (taken care of in hardware). However, the ...
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... T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu Preliminary Value on Value on Bit 1 Bit 0 Power-on all other Reset RESETS INTF RBIF 0000 000x 0000 000u TMR2IF TMR1IF 00-- 0000 00-- 0000 TMR2IE TMR1IE 00-- 0000 00-- 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 2001 Microchip Technology Inc. ...
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... TMR2IF, (PIR1<1>)). Timer2 can be shut-off by clearing control bit TMR2ON (T2CON<2>) to minimize power consumption. Figure 7-1 shows the Timer2 control register. 2001 Microchip Technology Inc. 7.1 Timer2 Prescaler and Postscaler The prescaler and postscaler counters are cleared when any of the following occurs: • ...
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... R/W-0 R/W-0 R/W-0 bit Bit is unknown Value on Value on Bit 1 Bit 0 Power-on all other Reset RESETS INTF RBIF 0000 000x 0000 000u TMR2IF TMR1IF 00-- 0000 00-- 0000 TMR2IE TMR1IE 00-- 0000 00-- 0000 0000 0000 0000 0000 1111 1111 1111 1111 2001 Microchip Technology Inc. ...
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... Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1) 11xx = PWM mode Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. Register 8-1 shows the CCP1CON register. For use of the CCP module, refer to the Embedded Control Handbook, “Using the CCP Modules” (AN594). TABLE 8-1: ...
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... EXAMPLE 8-1: CLRF CCP1CON MOVLW NEW_CAPT_PS ; Load the W reg with MOVWF CCP1CON CCPR1L TMR1L Preliminary CHANGING BETWEEN CAPTURE PRESCALERS ; Turn CCP module off ; the new prescaler ; mode value and CCP ON ; Load CCP1CON with ; this value 2001 Microchip Technology Inc. ...
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... Clearing the CCP1CON register will force the RC2/CCP1 compare output latch to the default low level. This is not the PORTC I/O data latch. 2001 Microchip Technology Inc. 8.2.2 TIMER1 MODE SELECTION Timer1 must be running in Timer mode, or Synchro- nized Counter mode, if the CCP module is using the compare feature ...
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... Note: If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared. Preliminary • OSC (TMR2 prescale value) 10-bit value is represented by T • (TMR2 prescale value) OSC F OSC --------------- log F PWM = -----------------------------bits log 2 2001 Microchip Technology Inc. ...
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... TABLE 8-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 8 MHz PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) 2001 Microchip Technology Inc. PIC16C925/926 • MHz • 1 • 125 ns • 1 8.3.3 SET-UP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1 ...
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... Power-on all other Reset RESETS INTF RBIF 0000 000x 0000 000u TMR2IF TMR1IF 00-- 0000 00-- 0000 TMR2IE TMR1IE 00-- 0000 00-- 0000 --11 1111 --11 1111 0000 0000 0000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 2001 Microchip Technology Inc. ...
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... Transmit (I C mode only Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. • Serial Peripheral Interface (SPI • Inter-Integrated Circuit (I Refer to Application Note AN578, "Use of the SSP Module in the I R-0 R-0 R-0 ...
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... Value at POR DS39544A-page 60 R/W-0 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 SSPM2 /4 OSC /16 OSC /64 OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Preliminary R/W-0 R/W-0 SSPM1 SSPM0 bit Bit is unknown 2001 Microchip Technology Inc. ...
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... Example 9-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The MOVWF RXDATA instruction (shaded) is only required if the received data is meaningful. 2001 Microchip Technology Inc. PIC16C925/926 EXAMPLE 9-1: BCF BSF LOOP ...
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... In SLEEP mode, the slave can transmit and receive data and wake the device from SLEEP. SPI Slave SSPM3:SSPM0 = 010x b SDO SDI SDI SDO LSb Serial Clock SCK SCK Preliminary ) Serial Input Buffer (SSPBUF) Shift Register (SSPSR) MSb LSb PROCESSOR 2 2001 Microchip Technology Inc. ...
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... SCK (CKP = 0) SCK (CKP = 1) bit7 SDO SDI (SMP = 0) bit7 SSPIF 2001 Microchip Technology Inc. PIC16C925/926 Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = 0100), the SPI module will reset if the SS pin is set the SPI is used in Slave mode with CKE = ’ ...
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... Preliminary bit1 bit0 bit0 Value on Value on all Bit 0 Power-on other Reset RESETS RBIF 0000 000x 0000 000u 00-- 0000 00-- 0000 xxxx xxxx uuuu uuuu SSPM0 0000 0000 0000 0000 --11 1111 --11 1111 --11 1111 --11 1111 UA BF 0000 0000 0000 0000 2001 Microchip Technology Inc. ...
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... Synchronization Procedure where the clock signals of two or more devices are synchronized. 2001 Microchip Technology Inc. The output stages of the clock (SCL) and data (SDA) lines must have an open drain or open collector, in order to perform the wired-AND function of the bus. ...
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... Byte Complete Interrupt with Receiver Clock Line Held Low while Interrupts are Serviced R/W ACK Wait Data State Preliminary SLAVE-RECEIVER ACKNOWLEDGE Not Acknowledge Acknowledge Clock Pulse for Acknowledgment Acknowledgment Signal from Receiver STOP ACK Condition 2001 Microchip Technology Inc. ...
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... A = Not Acknowledge (SDA high) From master to slave S = START Condition From slave to master P = STOP Condition 2001 Microchip Technology Inc. PIC16C925/926 while SCL is high), but occurs after a data transfer Acknowledge pulse (not the bus-free state). This allows a master to send “commands” to the slave and then receive the requested information address a dif- ferent slave device ...
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... SCL line low. The SCL line high time is determined by the device with the shortest high period, Figure 9-15. FIGURE 9-15: CLOCK SYNCHRONIZATION CLK 1 Counter CLK Reset 2 SCL Preliminary Start Counting Wait State HIGH Period 2001 Microchip Technology Inc. ...
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... SSP Status Register (SSPSTAT) • Serial Receive/Transmit Buffer (SSPBUF) • SSP Shift Register (SSPSR) - Not directly accessible • SSP Address Register (SSPADD) 2001 Microchip Technology Inc. The SSPCON register allows control of the I tion. Four mode selection bits (SSPCON<3:0>) allow one of the following I 2 • ...
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... Receive first (high) byte of Address (bits SSPIF and BF are set). 9. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Generate ACK SSPBUF Pulse Yes Yes Preliminary Set bit SSPIF (SSP Interrupt occurs if enabled) Yes Yes Yes Yes 2001 Microchip Technology Inc. ...
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... Data in sampled SSPIF (PIR1<3>) BF (SSPSTAT<0>) CKP (SSPCON<4>) 2001 Microchip Technology Inc. When the address byte overflow condition exists, then no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set, or bit SSPOV (SSPCON<6>) is set. An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1< ...
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... Value on Value on all Bit 0 Power-on other Reset RESETS RBIF 0000 000x 0000 000u 00-- 0000 00-- 0000 00-- 0000 00-- 0000 xxxx xxxx uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 BF 0000 0000 0000 0000 --11 1111 --11 1111 2 C mode. 2001 Microchip Technology Inc. ...
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... Set interrupt; Set (Low_byte_addr_match else if (High_byte_addr_match AND (R (PRIOR_ADDR_MATCH) { send ACK = 0; set XMIT_MODE; } else PRIOR_ADDR_MATCH = FALSE; } 2001 Microchip Technology Inc MODULE IN IDLE_MODE, RCV_MODE OR XMIT_MODE Set interrupt Send ACK = 0; set XMIT_MODE; } else if (R set RCV_MODE; End of transmission; Go back to IDLE_MODE; { PRIOR_ADDR_MATCH = TRUE; ...
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... PIC16C925/926 NOTES: DS39544A-page 74 Preliminary 2001 Microchip Technology Inc. ...
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... A/D converter module is operating 0 = A/D converter module is shut-off and consumes no operating current Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. PIC16C925/926 The A/D module has four registers. These registers are: • A/D Result High Register (ADRESH) • A/D Result Low Register (ADRESL) • ...
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... Preliminary R/W-0 R/W-0 R/W-0 PCFG2 PCFG1 PCFG0 bit HAN REF REF (1) Refs RA3 RA3 RA3 RA3 RA2 3 5 RA3 V 4/1 SS RA3 RA2 3/2 RA3 RA2 3/2 RA3 RA2 2 1 RA3 RA2 1 Bit is unknown 2001 Microchip Technology Inc. ...
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... A/D BLOCK DIAGRAM V REF A/D Converter (Reference Voltage) V REF (Reference Voltage) 2001 Microchip Technology Inc. 3. Wait the required acquisition time. 4. Start conversion: • Set GO/DONE bit (ADCON0) 5. Wait for A/D conversion to complete, by either: • Polling for the GO/DONE bit to be cleared (interrupts disabled) OR • ...
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... HOLD delay must complete before acquisition can begin again Sampling Switch LEAKAGE V = 0.6V T ± 500 Preliminary the minimum acquisition time, , see ACQ Mid-Range Reference Manual SS C HOLD = DAC Capacitance = 120 Sampling Switch (k ) 2001 Microchip Technology Inc. ...
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... When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only recom- mended for SLEEP operation. 3: For extended voltage devices (LC), please refer to the Electrical Specifications section. 2001 Microchip Technology Inc. PIC16C925/926 For correct A/D conversions, the A/D conversion clock ...
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... A/D. CYCLES ADRES is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input wait is necessary before the next AD acquisition is started. Preliminary wait is required before the next AD wait, acquisition AD and a maximum 2001 Microchip Technology Inc. ...
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... PORTA Data Latch when written: PORTA pins when read Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used for A/D conversion. Note 1: These bits are reserved; always maintain these bits clear. 2001 Microchip Technology Inc. 10-Bit Result 0 7 ADRESH ...
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... PIC16C925/926 NOTES: DS39544A-page 82 Preliminary 2001 Microchip Technology Inc. ...
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... Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. PIC16C925/926 selecting the number of commons required by the LCD panel, and then specifying the LCD frame clock rate to be used by the panel. Once the module is initialized for the LCD panel, the individual bits of the LCD data registers are cleared/set to represent a clear/dark pixel, respectively ...
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... Clock source/(96 * (LP3:LP0 + 1)) 1/4 Clock source/(128 * (LP3:LP0 + 1 Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Preliminary To I/O Pads R/W-0 R/W-0 R/W-0 LP2 LP1 LP0 bit 0 Frame Frequency x = Bit is unknown 2001 Microchip Technology Inc. ...
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... FIGURE 11-2: WAVEFORMS IN STATIC DRIVE Liquid Crystal Display and Terminal Connection COM0 SEG7 SEG6 SEG5 Selected Waveform COM0 - SEG1 Non-selected Waveform 2001 Microchip Technology Inc. PIN COM0 PIN SEG0 PIN SEG1 COM0 - SEG0 1 frame t f Preliminary PIC16C925/926 1/1 V 0/1 V 1/1 V 0/1 V ...
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... COM0 - SEG0 Selected Waveform COM0 - SEG1 Non-selected Waveform DS39544A-page 86 PIN COM0 PIN COM1 PIN SEG0 PIN SEG1 1 frame t f Preliminary 2/2 V 1/2 V 0/2 V 2/2 V 1/2 V 0/2 V 2/2 V 0/2 V 2/2 V 0/2 V 2/2 V 1/2 V 0/2 V -1/2 V -2/2 V 2/2 V 0/2 V -2/2 V 2001 Microchip Technology Inc. ...
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... WAVEFORMS IN ONE-THIRD DUTY CYCLE DRIVE (B TYPE) Liquid Crystal Display and Terminal Connection COM2 COM1 COM0 SEG0 SEG2 SEG1 COM0 - SEG1 Selected Waveform COM0 - SEG0 Non-selected Waveform 2001 Microchip Technology Inc. PIC16C925/926 PIN COM0 PIN COM1 PIN COM2 PIN SEG0 PIN SEG1 1 frame ...
Page 90
... Preliminary 3/3 V 2/3 V 1/3 V 0/3 V 3/3 V 2/3 V 1/3 V 0/3 V 3/3 V 2/3 V 1/3 V 0/3 V 3/3 V 2/3 V 1/3 V 0/3 V 3/3 V 2/3 V 1/3 V 0/3 V 3/3 V 2/3 V 1/3 V 0/3 V 3/3 V 2/3 V 1/3 V 0/3 V -1/3 V -2/3 V -3/3 V 1/3 V 0/3 V -1/3 V 2001 Microchip Technology Inc. ...
Page 91
... Internal RC Oscillator CS1:CS0 Nominal kHz RC 2001 Microchip Technology Inc. PIC16C925/926 The second source is the Timer1 external oscillator. This oscillator provides a lower speed clock which may be used to continue running the LCD while the proces- sor is in SLEEP assumed that the frequency pro- vided on this oscillator will be 32 kHz ...
Page 92
... APPROXIMATE FRAME FREQUENCY (IN Hz) USING TIMER1 @ 32.768 kHz OR F OSC LP3:LP0 Static TABLE 11-3: APPROXIMATE FRAME FREQUENCY (IN Hz) USING INTERNAL RC OSC @ 14 kHz LP3:LP0 Static 109 Preliminary @ 8 MHz 1/2 1/3 1/4 85 114 1/2 1/3 1/4 109 146 109 2001 Microchip Technology Inc. ...
Page 93
... ( ns)) FWR CY 2001 Microchip Technology Inc. PIC16C925/926 A new frame is defined to begin at the leading edge of the COM0 common signal. The interrupt will be set immediately after the LCD controller completes accessing all pixel data required for a frame. This will occur at a fixed interval before the frame boundary ( shown in Figure 11-7 ...
Page 94
... R/W-x R/W-x R/W-x R/W-x SEGs SEGs SEGs SEGs COMc COMc COMc COMc W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Preliminary R/W-x R/W-x SEGs SEGs COMc COMc bit Bit is unknown 2001 Microchip Technology Inc. ...
Page 95
... Pin SEG0 Interrupted Frame SLEEP Instruction Execution 2001 Microchip Technology Inc. PIC16C925/926 If a SLEEP instruction is executed and SLPEN = ’0’, the module will continue to display the current contents of the LCDD registers. To allow the module to continue operation while in SLEEP, the clock source must be either the internal RC oscillator or Timer1 external oscillator ...
Page 96
... Bit is set ’0’ = Bit is cleared Preliminary ;Select Bank 2 ; ;Make PortD,E,F,G ;LCD pins ;configure rest of LCD ;Select Bank 2 ; ;Make PORTD<7:0> & ;PORTE<6:0> LCD pins ;configure rest of LCD R/W-1 R/W-1 R/W-1 SE9 SE5 SE0 bit Bit is unknown 2001 Microchip Technology Inc. ...
Page 97
... F* 130 LCD V 3 LCD * These values are provided for design guidance only and should be optimized to the application by the designer. 2001 Microchip Technology Inc. PIC16C925/926 pump. The charge pump boosts V 2*V 1 and LCD LCD pump is not operating, Vlcd3 will be internally tied to V ...
Page 98
... COM3 COM3 SEG17 SEG16 xxxx xxxx uuuu uuuu COM3 COM3 SEG25 SEG24 xxxx xxxx uuuu uuuu COM3 COM3 SE5 SE0 1111 1111 1111 1111 LP1 LP0 ---- 0000 ---- 0000 LMUX1 LMUX0 00-0 0000 00-0 0000 2001 Microchip Technology Inc. ...
Page 99
... RESET until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay (nomi- nal) on power-up only, designed to keep the part in 2001 Microchip Technology Inc. PIC16C925/926 RESET while the power supply stabilizes. With these two timers on-chip, most applications need no external RESET circuitry ...
Page 100
... BOREN: Brown-out Reset Enable bit 1 = BOR enabled 0 = BOR disabled bit 5-4 CP1:CP0: Program Memory Code Protection bits PIC16C926 (8K program memory Code protection off 10 = 0000h to 0FFFh code protected (1/2 protected 0000h to 1EFFh code protected (all but last 256 protected 0000h to 1FFFh code protected (all protected) ...
Page 101
... FIGURE 12-2: EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) OSC1 Clock from Ext. System PIC16CXXX OSC2 Open 2001 Microchip Technology Inc. TABLE 12-1: Mode XT HS These values are for design guidance only. See notes following Table 12-2. TABLE 12-2: Osc Type The LP ...
Page 102
... Figure 1-2 for waveform). FIGURE 12- EXT To Other Devices C EXT CLKIN V SS PIC16CXXX Preliminary ) values, and the operat- EXT values EXT values EXT = 0 pF), we recommend using values for given OSCILLATOR MODE Internal OSC1 Clock PIC16CXXX OSC2/CLKOUT F /4 OSC 2001 Microchip Technology Inc. ...
Page 103
... Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. 2: See Table 12-3 for various time-out situations. 2001 Microchip Technology Inc. PIC16C925/926 SLEEP. They are not affected by a WDT Wake-up, which is viewed as the resumption of normal operation. The TO and PD bits are set or cleared differently in dif- ferent RESET situations, as indicated in Table 12-4 ...
Page 104
... Preliminary falls below V DD BOR BOR falls below V for less DD BOR rises above V . The DD BOR (parameter #33, about 72mS). If PWRT during T , the BOR PWRT rises DD with the Power-up Timer Reset. The Wake-up from SLEEP 1024 T OSC OSC — 2001 Microchip Technology Inc. ...
Page 105
... Brown-out Reset Interrupt wake-up from SLEEP Legend unchanged unknown unimplemented bit, read as ’0’. Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 2001 Microchip Technology Inc. PIC16C925/926 Condition Program STATUS ...
Page 106
... Microchip Technology Inc. ...
Page 107
... Note 1: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 12-5 for RESET value for specific condition. 2001 Microchip Technology Inc. PIC16C925/926 MCLR Resets WDT Reset ...
Page 108
... V DD MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 12-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS39544A-page 106 T PWRT T OST T PWRT T OST T PWRT T OST Preliminary ): CASE CASE 2001 Microchip Technology Inc. ...
Page 109
... CCP1IF CCP1IE SSPIF SSPIE ADIF ADIE 2001 Microchip Technology Inc. PIC16C925/926 The “return from interrupt” instruction, RETFIE, exits the interrupt routine as well as sets the GIE bit, which re-enables interrupts. The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register ...
Page 110
... An input change on PORTB<7:4> sets flag bit RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit, RBIE (INTCON<4>) (Section 4.2). Preliminary 0004h 0005h Inst (0004h) Inst (0005h) Inst (0004h) Dummy Cycle 00h) in the TMR0 register will set by setting/clearing enable bit, 2001 Microchip Technology Inc. ...
Page 111
... MOVF PCLATH_TEMP, W MOVWF PCLATH SWAPF STATUS_TEMP,W MOVWF STATUS SWAPF W_TEMP,F SWAPF W_TEMP,W 2001 Microchip Technology Inc. PIC16C925/926 The code in the example: e) Stores the W register. f) Stores the STATUS register in bank 0. g) Stores the PCLATH register. h) Executes the ISR code. i) Restores the STATUS register (and bank select bit) ...
Page 112
... MUX WDT Time-out Bit 6 Bit 5 Bit 4 Bit 3 (1) BOREN CP1 CP0 PWRTE INTEDG T0CS T0SE PSA Preliminary = Min., Temperature = Max., and DD PS2:PS0 To TMR0 (Figure 5-6) PSA Bit 2 Bit 1 Bit 0 (1) WDTE FOSC1 FOSC0 PS2 PS1 PS0 2001 Microchip Technology Inc. ...
Page 113
... Special event trigger (Timer1 in Asynchronous mode using an external clock). 7. LCD module. 2001 Microchip Technology Inc. PIC16C925/926 Other peripherals can not generate interrupts since during SLEEP, no on-chip Q clocks are present. When the SLEEP instruction is being executed, the next instruction ( pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled) ...
Page 114
... PIC16C6X/7X Programming Specifications (Literature #DS30228). FIGURE 12-15: External Connector Signals + CLK Data I/O Preliminary 0004h 0005h Inst(0004h) Inst(0005h) Dummy cycle Inst(0004h) TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION To Normal Connections PIC16CXXX MCLR/V PP RB6 RB7 Normal Connections 2001 Microchip Technology Inc. ...
Page 115
... OPCODE k (literal 8-bit immediate value CALL and GOTO instructions only OPCODE k (literal 11-bit immediate value 2001 Microchip Technology Inc. PIC16C925/926 TABLE 13-1: Field Register file address (0x00 to 0x7F) f Working register (accumulator) W operations. Bit address within an 8-bit file register b Literal field, constant data or label k Don’ ...
Page 116
... Z 1,2 ffff ffff 0000 C 1,2 ffff C 1,2 ffff C,DC,Z 1,2 ffff 1,2 ffff Z 1,2 ffff 1,2 ffff 1,2 ffff 3 ffff 3 ffff C,DC,Z kkkk Z kkkk kkkk 0100 kkkk Z kkkk kkkk 1001 kkkk 1000 0011 C,DC,Z kkkk Z kkkk 2001 Microchip Technology Inc. ...
Page 117
... Cycles Cycle Activity Decode Read Process literal ’k’ Example: ADDLW 0x15 Before Instruction 0x10 After Instruction 0x25 2001 Microchip Technology Inc. ADDWF Syntax: k Operands: Operation: Status Affected: kkkk kkkk Encoding: Description: Words: Cycles Cycle Activity: Write to data W Example Before Instruction: ...
Page 118
... AND the W register with register ’f’. If ’d’ the result is stored in the W register. If ’d’ the result is stored back in register ’f’ Read Process Write to Decode register data destination 'f' ANDWF FSR 0x17 = 0xC2 = 0x17 = 0x02 2001 Microchip Technology Inc. ...
Page 119
... Q2 Q Cycle Activity: Decode Read Process register ’f’ BSF FLAG_REG, Example Before Instruction: FLAG_REG = 0x0A After Instruction: FLAG_REG = 0x8A 2001 Microchip Technology Inc. BTFSC Syntax: Operands: Operation: Status Affected: bfff ffff Encoding: Description Write Words: data register ’f’ Cycles: ...
Page 120
... The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction Read literal ’k’, Process Write to Decode Push PC data PC to Stack Operation Operation Operation Operation HERE CALL THERE = Address HERE = Address THERE = Address HERE+1 2001 Microchip Technology Inc. ...
Page 121
... Q Cycle Activity: Read Process Decode register ’f’ Example CLRF FLAG_REG Before Instruction: FLAG_REG = 0x5A After Instruction: FLAG_REG = 0x00 2001 Microchip Technology Inc. CLRW Syntax: Operands: Operation: Status Affected: 1fff ffff Encoding: Description: Words: Cycles Cycle Activity: Write register data ’f’ ...
Page 122
... The contents of register ’f’ are com- plemented. If ’d’ the result is stored ’d’ the result is stored back in register ’f’ Read Process Write to Decode register ’f’ data destination COMF REG1,0 = 0x13 = 0x13 = 0xEC 2001 Microchip Technology Inc. ...
Page 123
... Example 1 DECF CNT, Before Instruction: CNT = 0x01 After Instruction: CNT = 0x00 2001 Microchip Technology Inc. DECFSZ Syntax: Operands: Operation: Status Affected: dfff ffff Encoding: Description Write to Words: data destination Cycles: Q Cycle Activity: If Skip: (2nd Cycle) Example Before Instruction: ...
Page 124
... The contents of register ’f’ are incre- mented. If ’d’ the result is placed in the W register. If ’d’ the result is placed back in register ’f’ Read Process Write to Decode register data destination ’f’ INCF CNT 0xFF = 0 = 0x00 = 1 2001 Microchip Technology Inc. ...
Page 125
... Before Instruction address HERE After Instruction: CNT = CNT + 1 if CNT = address CONTINUE if CNT address HERE +1 2001 Microchip Technology Inc. IORLW Syntax: Operands: Operation: Status Affected: Encoding: Description: dfff ffff Words: Cycles: Q Cycle Activity: CY Example Q3 Q4 Before Instruction: Process Write to W ...
Page 126
... Move Literal label ] MOVLW 255 k (W) None 11 00xx kkkk kkkk The eight-bit literal ’k’ is loaded into W register. The don’t cares will assemble as 0’ Read Process Write to Decode literal ’k’ data W MOVLW 0x5A 0x5A 2001 Microchip Technology Inc. ...
Page 127
... Decode register ’f’ Example MOVWF OPTION_REG Before Instruction: OPTION = 0xFF W = 0x4F After Instruction: OPTION = 0x4F W = 0x4F 2001 Microchip Technology Inc. NOP f Syntax: Operands: Operation: Status Affected: 1fff ffff Encoding: Description: Words: Cycles: Q Cycle Activity Write data register ’f’ Example ...
Page 128
... Pop from literal ’k’ Operation the Stack Operation Operation Operation Operation CALL TABLE ;W contains table ;offset value ;W now has table value • • offset RETLW k1 ;Begin table RETLW k2 ; • • • RETLW kn ; End of table = 0x07 = value of k8 2001 Microchip Technology Inc ...
Page 129
... Words: 1 Cycles Cycle Activity: No 1st Cycle Decode Operation No No 2nd Cycle Operation Operation Example RETURN After Interrupt TOS 2001 Microchip Technology Inc. RLF Syntax: Operands: Operation: Status Affected: 0000 1000 Encoding: Description Words: No Pop from Operation the Stack Cycles Cycle Activity: ...
Page 130
... The power-down status bit cleared. Time-out status bit set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. See Section 12.8 for more details Decode Operation Operation Sleep SLEEP 2001 Microchip Technology Inc. ...
Page 131
... result is zero Example 3: Before Instruction After Instruction 0xFF result is negative 2001 Microchip Technology Inc. SUBWF Syntax: Operands: Operation: Status Affected: kkkk kkkk Encoding: Description: Words: Cycles Cycle Activity: Process Write to W data Example 1: Before Instruction: REG1 After Instruction: REG1 Example 2: Before Instruction: ...
Page 132
... The instruction is supported for code compatibility with the PIC16C5X products. Since TRIS registers are readable and writ- able, the user can directly address them maintain upward compatibil- ity with future PIC16CXXX products, do not use this instruction. 2001 Microchip Technology Inc. ...
Page 133
... Cycles Cycle Activity: Decode Read literal ’k’ Example: XORLW 0xAF Before Instruction 0xB5 After Instruction 0x1A 2001 Microchip Technology Inc. XORWF Syntax: Operands: Operation: Status Affected: kkkk kkkk Encoding: Description: Words Cycles: Process Write to Q Cycle Activity: data W Example Before Instruction: ...
Page 134
... PIC16C925/926 NOTES: DS39544A-page 132 Preliminary 2001 Microchip Technology Inc. ...
Page 135
... A project manager • Customizable toolbar and key mapping • A status bar • On-line help 2001 Microchip Technology Inc. PIC16C925/926 The MPLAB IDE allows you to: • Edit your source files (either assembly or ‘C’) • One touch assemble (or compile) and download ...
Page 136
... ICEPIC In-Circuit Emulator The ICEPIC low cost, in-circuit emulator is a solution for the Microchip Technology PIC16C5X, PIC16C6X, PIC16C7X and PIC16CXXX families of 8-bit One- Time-Programmable (OTP) microcontrollers. The mod- ular system can support different subsets of PIC16C5X or PIC16CXXX products through the use of inter- changeable personality modules, or daughter boards ...
Page 137
... PIC16C92X PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant. 2001 Microchip Technology Inc. 14.11 PICDEM 1 Low Cost PICmicro Demonstration Board The PICDEM 1 demonstration board is a simple board which demonstrates the capabilities of several of Microchip’s microcontrollers. The microcontrollers sup- ...
Page 138
... Programming Tools K L evaluation and programming tools support EE OQ Microchip’s HCS Secure Data Products. The HCS eval- uation kit includes a LCD display to show changing codes, a decoder to decode transmissions and a pro- gramming interface to program test transmitters. Preliminary 2001 Microchip Technology Inc. ...
Page 139
... PIC16C6X á á á á PIC16C5X á á á PIC14000 á á á á PIC12CXXX Tools Software Emulators 2001 Microchip Technology Inc. á á á á á á á á á á á á á á á á á á ...
Page 140
... PIC16C925/926 NOTES: DS39544A-page 138 Preliminary 2001 Microchip Technology Inc. ...
Page 141
... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2001 Microchip Technology Inc. (except V , MCLR, and RA4) ......................................... -0. ...
Page 142
... V 3.0 V 2 (6.0 MHz/V) (V MAX Note the minimum voltage of the PICmicro DDAPPMIN Note 2: F has a maximum frequency of 10MHz. MAX DS39544A-page 140 PIC16C925/926 Frequency PIC16LC925/926 10 MHz 4 MHz Frequency - 2 MHz DDAPPMIN ® Preliminary 20 MHz device in the application. 2001 Microchip Technology Inc. ...
Page 143
... LCD Module and the voltage generation LCDT LCDRC circuitry. This does not include current dissipated by the LCD panel. 2001 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C 0°C Standard Operating Conditions (unless otherwise stated) Operating temperature -40° ...
Page 144
... R in kOhm. EXT EXT measurement. Preliminary T +85°C for industrial A T +70°C for commercial A T +85°C for industrial A T +70°C for commercial A Conditions = 3.0V = 4.0V = 3.0V = 4.0V = 3.0V (Note 7) = 4.0V (Note 3.0V (Note 7) = 4.0V (Note 7) and 2001 Microchip Technology Inc. ...
Page 145
... LCD Module and the voltage generation LCDT LCDRC circuitry. This does not include current dissipated by the LCD panel. 2001 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C 0°C Standard Operating Conditions (unless otherwise stated) Operating temperature -40° ...
Page 146
... OSC1. — — — — 400 pF — — 8.5 V RA4 pin Preliminary +85°C for industrial +70°C for commercial Conditions range 5.5V DD range PIN Pin at hi-Z PIN DD V PIN XT, HS and LP PIN 4.5V DD 2001 Microchip Technology Inc. ...
Page 147
... No. D250 I VLCDADJ Regulated Current Output VADJ D252 VLCDADJ Current V VADJ DD D265 V VLCDADJ Voltage VADJ Limits Note 1: For design guidance only. 2001 Microchip Technology Inc. PIC16C925/926 D224 Min Typ† Max V - 0.3 — Vss + 7.0 DD Vss - 0.3 — LCD Vss - 0.3 — ...
Page 148
... OSC2 unless otherwise noted for OSC2 output DS39544A-page 146 specifications only specifications only) T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise V Valid Z Hi-impedance High High Low Low SU Setup STO STOP condition Load condition Pin V SS Preliminary 2001 Microchip Technology Inc. ...
Page 149
... All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices. 2001 Microchip Technology Inc ...
Page 150
... Max Units Conditions 75 200 ns (Note 1) 75 200 ns (Note 1) 35 100 ns (Note 1) 35 100 ns (Note 1) — 0. (Note 1) CY — — ns (Note 1) — — ns (Note 1) 50 150 ns — — ns — — ns — — — — — — ns — — ns 2001 Microchip Technology Inc. ...
Page 151
... T I/O Hi-impedance from MCLR Low IOZ or Watchdog Timer Reset † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2001 Microchip Technology Inc. PIC16C925/926 Min Typ† Max ...
Page 152
... N = prescale value (2, 4,..., 256) — ns Must also meet parameter 47 — ns — ns — ns — ns — ns — ns Must also meet — ns parameter 47 — ns — prescale value — prescale value ( — ns — ns 200 kHz 7Tosc — 2001 Microchip Technology Inc. ...
Page 153
... With Prescaler PIC16C925/926 52 TccP Input Period 53 TccR Output Rise Time 54 TccF Output Fall Time † Data in “Typ” column 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2001 Microchip Technology Inc. PIC16C925/926 Min 0. PIC16LC925/926 20 0 ...
Page 154
... FIGURE 15-11: SPI MASTER MODE TIMING (CKE = SCK (CKP = SCK (CKP = 1) SDO MSb SDI MSb IN 74 Note: Refer to Figure 15-4 for load conditions. DS39544A-page 152 MSb BIT6 - - - - - -1 75, 76 BIT6 - - - - LSb BIT6 - - - - - -1 75, 76 BIT6 - - - -1 LSb IN Preliminary 79 78 LSb LSb 2001 Microchip Technology Inc. ...
Page 155
... FIGURE 15-13: SPI SLAVE MODE TIMING (CKE = SCK (CKP = 0) 71 SCK (CKP = 1) MSb SDO SDI SDI MSb IN 74 Note: Refer to Figure 15-4 for load conditions. 2001 Microchip Technology Inc MSb BIT6 - - - - - -1 75, 76 MSb IN BIT6 - - - - BIT6 - - - - - -1 LSb 75, 76 BIT6 - - - -1 LSb IN Preliminary PIC16C925/926 ...
Page 156
... CY Single Byte — — 10 — — — — Preliminary Typ† Max Units Conditions — — ns — — ns — — ns — — ns — — ns — — — — — — ns — — — ns — — ns 2001 Microchip Technology Inc. ...
Page 157
... Hold time STOP condition SU STO Setup time STOP condition HD STO Hold time 2001 Microchip Technology Inc. PIC16C925/926 Min Typ Max Units 100 kHz mode 4700 — — ns 100 kHz mode 4000 — — ns 100 kHz mode 4700 — — ns 100 kHz mode 4000 — ...
Page 158
... Device must operate at a minimum of 1.5 MHz s Device must operate at a minimum of 1.5 MHz Only relevant for Repeated START condition s After this period the first clock pulse is generated (Note 1) s Time the bus must be free before a new transmission can start pF 2001 Microchip Technology Inc. ...
Page 159
... Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module current is from RA3 pin or V REF 2001 Microchip Technology Inc. PIC16C925/926 Min Typ† Max — ...
Page 160
... LSb (i.e 5.12V) from the last sam- pled voltage (as stated HOLD — If the A/D clock source is selected as RC, a time added CY before the A/D clock starts. This allows the SLEEP instruction to be executed 2001 Microchip Technology Inc. ...
Page 161
... DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs and Tables are not available at this time. 2001 Microchip Technology Inc. PIC16C925/926 Preliminary DS39544A-page 159 ...
Page 162
... PIC16C925/926 NOTES: DS39544A-page 160 Preliminary 2001 Microchip Technology Inc. ...
Page 163
... For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2001 Microchip Technology Inc. PIC16C925/926 Example PIC16C925 -I/PT 0010017 Example PIC16C926/L 0010017 Preliminary DS39544A-page 161 ...
Page 164
... PIC16C925/926 Package Marking Information (Continued) 68-Lead CERQUAD Windowed XXXXXXXXXXXXXXX YYWWNNN DS39544A-page 162 Example PIC16C926/CL 0010017 Preliminary 2001 Microchip Technology Inc. ...
Page 165
... Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-026 Drawing No. C04-085 2001 Microchip Technology Inc. PIC16C925/926 ...
Page 166
... Microchip Technology Inc. ...
Page 167
... Ceramic Package Length Footprint Width Footprint Length Pins each side Lead Thickness Upper Lead Width Lower Lead Width Window Diameter * Controlling Parameter § Significant Characteristic JEDEC Equivalent: MO-087 Drawing No. C04-097 2001 Microchip Technology Inc. PIC16C925/926 CH1 Units INCHES* MIN NOM MAX ...
Page 168
... PIC16C925/926 NOTES: DS39544A-page 166 Preliminary 2001 Microchip Technology Inc. ...
Page 169
... The differences between the devices listed in this data sheet are listed in Table B-1. TABLE B-1: DEVICE DIFFERENCES Feature PIC16C925 EPROM Program Memory (words) Data Memory (bytes) Note: On 64-pin TQFP, pins RG7 and RE7 are not available. Preliminary PIC16C926 4K 8K 176 336 DS39544A-page 167 ...
Page 170
... Data Memory 176 (bytes) A/D Converter 8-bit Resolution (924 only) A/D Converter none (923) Channels 5 (924) 8 (923) Interrupt Sources 9 (924) Brown-out Reset No DS39544A-page 168 PIC16C925/ 926 MHz 4K (925) 8K (926) 176 (925) 336 (926) 10-bit 5 9 Yes Preliminary 2001 Microchip Technology Inc. ...
Page 171
... LCD Module ............................................................... 84 LCD Resistor Ladder ................................................. 95 On-Chip Reset Circuit .............................................. 101 PIC16C925/926 Architecture ....................................... 6 PORTA RA3:RA0 and RA5 Port Pins ............................. 29 RA4/T0CKI Pin .................................................. 29 PORTB RB3:RB0 Port Pins ............................................ 31 RB7:RB4 Port Pins ............................................ 31 2001 Microchip Technology Inc. PIC16C925/926 PORTC ...................................................................... 33 PORTD Pins <4:0> ......................................................... 34 Pins <7:5> ......................................................... 34 PORTE ...................................................................... 36 PORTF ...................................................................... 37 PORTG ...................................................................... 38 PWM Mode ................................................................ 56 RC Oscillator ...
Page 172
... LCD Module Associated Registers ................................................. 96 Block Diagram ........................................................... 84 Charge Pump ............................................................ 95 Block Diagram ................................................... 95 Electrical Specifications ........................................... 145 External R-Ladder ...................................................... 95 Block Diagram ................................................... 95 Generic LCDD Register ............................................. 92 LCDCON Register ..................................................... 83 LCDPS Register ........................................................ 84 LCDSE Register ........................................................ 94 Register Initialization States .................................... 105 Voltage Generation .................................................... 95 Loading PC Register (Diagram) ......................................... 25 Preliminary 2 C. 2001 Microchip Technology Inc. ...
Page 173
... PICDEM 17 Demonstration Board ................................... 136 PICDEM 2 Low Cost PIC16CXX Demonstration Board ............................................... 135 PICDEM 3 Low Cost PIC16CXXX Demonstration Board ............................................... 136 PICSTART Plus Entry Level Development Programmer ....................................... 135 PIE1 Register ............................................................. 22, 107 Initialization States ................................................... 104 2001 Microchip Technology Inc. PIC16C925/926 Pin Functions MCLR/V ................................................................... 7 PP OSC1/CLKIN ............................................................... 7 OSC2/CLKOUT ........................................................... 7 RA0/AN0 ...................................................................... 7 RA1/AN1 ...
Page 174
... R/W bit ................................................................... 66, 70, 71 RBIF bit ...................................................................... 31, 108 RC Oscillator ...................................................... 99, 100, 102 RCV_MODE ...................................................................... 73 Read-Modify-Write ............................................................. 39 Register File ....................................................................... 12 Register File Map PIC16C925 ................................................................ 13 PIC16C926 ................................................................ 14 Registers ADCON0 (A/D Control 0) ........................................... 75 ADCON1 (A/D Control 1) ........................................... 76 CCP1CON (CCP Control) .......................................... 53 Flag ............................................................................ 23 Initialization Conditions .................................... 104–105 INTCON (Interrupt Control) ........................................ 21 LCDCON (LCD Control) ............................................ 83 LCDD (LCD Pixel Data, General Format) ...
Page 175
... SSPM3:SSPM0 .................................................................. 60 SSPOV (Receive Overflow Indicator) bit ........................... 60 SSPOV bit .......................................................................... 70 Stack .................................................................................. 25 Overflows ................................................................... 25 Underflow ................................................................... 25 STATUS Register .............................................................. 19 Initialization States ................................................... 104 Synchronous Serial Port Mode Select bits, SSPM3:SSPM0 .......................................................... 60 2001 Microchip Technology Inc. PIC16C925/926 T T .................................................................................... 79 AD Timer0 Associated Registers ................................................. 45 Block Diagram ........................................................... 41 Clock Source Edge Select (T0SE Bit) ....................... 20 Clock Source Select (T0CS Bit) ...
Page 176
... Associated Registers ............................................... 110 WDT Reset, Normal Operation ................................ 103 WDT Reset, SLEEP ................................................. 103 WCOL ................................................................................ 60 WDT Period ...................................................................... 110 Programming Considerations .................................. 110 Timeout .................................................................... 104 Write Collision Detect bit, WCOL ....................................... 60 WWW, On-Line Support .............................................. 4, 175 X XMIT_MODE ..................................................................... 73 XT .............................................................................. 99, 102 Z Z (Zero) bit ......................................................................... 19 Preliminary 2001 Microchip Technology Inc. ...
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... Microchip Products • Conferences for products, Development Systems, technical information and more • Listing of seminars and events 2001 Microchip Technology Inc. PIC16C925/926 Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip’ ...
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... Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS39544A-page 176 Total Pages Sent FAX: (______) _________ - _________ N Literature Number: DS39544A Preliminary 2001 Microchip Technology Inc. ...
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... Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2001 Microchip Technology Inc. /XX XXX Examples: Pattern a) PIC16C926/P 301 = Commercial Temp., normal V pattern #301 (2) b) PIC16LC925/PT ; Temp., TQFP package, extended (2) V ...
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... NOTES: 2001 Microchip Technology Inc. PIC16C925/926 Preliminary DS39544A-page 178 ...
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... NOTES: 2001 Microchip Technology Inc. PIC16C925/926 Preliminary DS39544A-page 179 ...
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... Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellec- tual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. ...