SST39SF010A-70-4I-WHE SILICON STORAGE TECHNOLOGY, SST39SF010A-70-4I-WHE Datasheet

SST39SF010A-70-4I-WHE

Manufacturer Part Number

SST39SF010A-70-4I-WHE

Description

MEMORY, FLASH, 1MBIT, PARL, 32TSOP

Manufacturer

SILICON STORAGE TECHNOLOGY

Datasheet

1.SST39SF020A-70-4C-NHE.pdf (25 pages)

Specifications of SST39SF010A-70-4I-WHE

Memory Size

1Mbit

Supply Voltage Range

4.5V To 5.5V

Memory Case Style

TSOP

No. Of Pins

Operating Temperature Range

-40Â°C To +85Â°C

Svhc

No SVHC (18-Jun-2010)

Access Time

70ns

Interface

Memory Type

Flash - NOR

Memory Configuration

128K X 8

Rohs Compliant

Yes

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Meier Automation Equipment Co., Limited

Part Number:

SST39SF010A-70-4I-WHE

Manufacturer:

SST

Quantity:

20 000

Company:

H&T Electronics

Part Number:

SST39SF010A-70-4I-WHE

Quantity:

5 000

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FEATURES:

• Organized as 128K x8 / 256K x8 / 512K x8

• Single 4.5-5.5V Read and Write Operations

• Superior Reliability

• Low Power Consumption

• Sector-Erase Capability

• Fast Read Access Time:

• Latched Address and Data

• Automatic Write Timing

PRODUCT DESCRIPTION

The SST39SF010A/020A/040 are CMOS Multi-Purpose

Flash (MPF) manufactured with SST’s proprietary, high

performance CMOS SuperFlash technology. The split-gate

cell design and thick oxide tunneling injector attain better

reliability and manufacturability compared with alternate

approaches. The SST39SF010A/020A/040 devices write

(Program or Erase) with a 4.5-5.5V power supply. The

SST39SF010A/020A/040 devices conform to JEDEC stan-

dard pinouts for x8 memories.

Featuring

SST39SF010A/020A/040 devices provide a maximum

Byte-Program time of 20 µsec. These devices use Toggle

Bit or Data# Polling to indicate the completion of Program

operation. To protect against inadvertent write, they have

on-chip hardware and Software Data Protection schemes.

Designed, manufactured, and tested for a wide spectrum of

applications, these devices are offered with a guaranteed

typical endurance of 100,000 cycles. Data retention is rated

at greater than 100 years.

The SST39SF010A/020A/040 devices are suited for appli-

cations that require convenient and economical updating of

program, configuration, or data memory. For all system

applications, they significantly improve performance and

reliability, while lowering power consumption. They inher-

ently use less energy during erase and program than alter-

native flash technologies. The total energy consumed is a

S71147-09-000

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

(typical values at 14 MHz)

– Active Current: 10 mA (typical)

– Standby Current: 30 µA (typical)

– Uniform 4 KByte sectors

– 55 ns

– 70 ns

– Internal V

1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash

high

Generation

SST39SF010A / 020A / 0405.0V 1Mb / 2Mb / 4Mb (x8) MPF memories

performance

01/10

SST39SF010A / SST39SF020A / SST39SF040

Byte-Program,

the

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

• Fast Erase and Byte-Program

• End-of-Write Detection

• TTL I/O Compatibility

• JEDEC Standard

• Packages Available

• All devices are RoHS compliant

• All non-Pb (lead-free) devices are RoHS compliant

function of the applied voltage, current, and time of applica-

tion. Since for any given voltage range, the SuperFlash

technology uses less current to program and has a shorter

erase time, the total energy consumed during any Erase or

Program operation is less than alternative flash technolo-

gies. These devices also improve flexibility while lowering

the cost for program, data, and configuration storage appli-

cations.

The SuperFlash technology provides fixed Erase and Pro-

gram times, independent of the number of Erase/Program

cycles that have occurred. Therefore the system software

or hardware does not have to be modified or de-rated as is

necessary with alternative flash technologies, whose Erase

and Program times increase with accumulated Erase/Pro-

gram cycles.

To meet high density, surface mount requirements, the

SST39SF010A/020A/040 are offered in 32-lead PLCC and

32-lead TSOP packages. A 600 mil, 32-pin PDIP is also

available. See Figures 2, 3, and 4 for pin assignments.

– Sector-Erase Time: 18 ms (typical)

– Chip-Erase Time: 70 ms (typical)

– Byte-Program Time: 14 µs (typical)

– Chip Rewrite Time:

– Toggle Bit

– Data# Polling

– Flash EEPROM Pinouts and command sets

– 32-lead PLCC

– 32-lead TSOP (8mm x 14mm)

– 32-pin PDIP

2 seconds (typical) for SST39SF010A

4 seconds (typical) for SST39SF020A

8 seconds (typical) for SST39SF040

These specifications are subject to change without notice.

MPF is a trademark of Silicon Storage Technology, Inc.

Data Sheet

Related parts for SST39SF010A-70-4I-WHE

SST39SF010A-70-4I-WHE Summary of contents

Page 1

... Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 SST39SF010A / 020A / 0405.0V 1Mb / 2Mb / 4Mb (x8) MPF memories FEATURES: • Organized as 128K x8 / 256K x8 / 512K x8 • Single 4.5-5.5V Read and Write Operations • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • ...

Page 2

... CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. Read The Read operation of the SST39SF010A/020A/040 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is dese- lected and only standby power is consumed ...

Page 3

... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data# Polling ( When the SST39SF010A/020A/040 are in the internal Pro- gram operation, any attempt to read DQ complement of the true data. Once the Program operation is completed, DQ will produce true data. Note that even 7 though DQ may have valid data immediately following the ...

Page 4

... Address Buffers & Latches CE# OE# WE# FIGURE 1: Functional Block Diagram SST39SF040 SST39SF020A DQ0 DQ0 FIGURE 2: Pin Assignments for 32-lead PLCC ©2010 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 X-Decoder Control Logic SST39SF010A 32-lead PLCC Top View 10 24 ...

Page 5

... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 SST39SF040 SST39SF020A SST39SF010A A11 A11 A11 A13 A13 A13 A14 A14 A14 A17 A17 NC WE# WE# WE A18 NC NC A16 A16 A16 A15 A15 A15 A12 A12 A12 FIGURE 3: Pin Assignments for 32-lead TSOP (8mm x 14mm) ...

Page 6

... TABLE 3: Operation Modes Selection Mode Read Program Erase Standby Write Inhibit Product Identification Software Mode 1. X can but no other value ©2010 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 -A address lines will select the sector for SST39SF040 18 CE# OE# WE ...

Page 7

... SST Manufacturer’ BFH, is read with SST39SF010A Device ID = B5H, is read with A SST39SF020A Device ID = B6H, is read with A SST39SF040 Device ID = B7H, is read with A 6. Both Software ID Exit operations are equivalent Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” ...

Page 8

... This parameter is measured only for initial qualification and after a design or process change that could affect this parameter endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a END higher minimum specification. ©2010 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 1 = 4.5-5.5V DD Limits Min Max ...

Page 9

... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 AC CHARACTERISTICS TABLE 9: Read Cycle Timing Parameters V Symbol Parameter T Read Cycle Time RC T Chip Enable Access Time CE T Address Access Time AA T Output Enable Access Time CE# Low to Active Output CLZ 1 T OE# Low to Active Output ...

Page 10

... OE# CE 7-0 SW0 Note Most significant address for SST39SF010A FIGURE 6: WE# Controlled Program Cycle Timing Diagram ©2010 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 OLZ T T CLZ DATA VALID for SST39SF020A, and A for SST39SF040 17 18 INTERNAL PROGRAM OPERATION STARTS ...

Page 11

... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 5555 ADDRESS CPH AS OE# WE 7-0 SW0 Note Most significant address for SST39SF010A FIGURE 7: CE# Controlled Program Cycle Timing Diagram ADDRESS A MS-0 CE# OE# WE Note Most significant address for SST39SF010A FIGURE 8: Data# Polling Timing Diagram © ...

Page 12

... Table 10 Sector Address Most significant address for SST39SF010A FIGURE 10: WE# Controlled Sector-Erase Timing Diagram ©2010 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 OEH T OE Note for SST39SF020A, and SIX-BYTE CODE FOR SECTOR-ERASE 5555 5555 2AAA ...

Page 13

... Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 10 Sector Address Most significant address for SST39SF010A for SST39SF020A, and A 18 for SST39SF040 FIGURE 11: WE# Controlled Chip-Erase Timing Diagram Three-byte Sequence for Software ID Entry ...

Page 14

... THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET 5555 2AAA ADDRESS A 14 7-0 CE# OE WE# SW0 FIGURE 13: Software ID Exit and Reset ©2010 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 5555 IDA T WHP SW1 SW2 14 1147 F10.0 S71147-09-000 01/10 ...

Page 15

... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 V IHT INPUT V ILT AC test inputs are driven at V (3.0V) for a logic “1” and V IHT and outputs are V (1.5V) and FIGURE 14: AC Input/Output Reference Waveforms TO DUT FIGURE 15: A Test Load Example ©2010 Silicon Storage Technology, Inc. ...

Page 16

... Data Sheet FIGURE 16: Byte-Program Algorithm ©2010 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Start Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: A0H Address: 5555H Load Byte Address/Byte Data Wait for end of ...

Page 17

... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Internal Timer Byte Program/Erase Initiated Wait SCE Program/Erase Completed FIGURE 17: Wait Options ©2010 Silicon Storage Technology, Inc. Toggle Bit Byte Program/Erase Initiated Read byte Read same No byte No Does DQ 6 match? Yes Program/Erase Completed ...

Page 18

... Address: 5555H Wait T IDA Read Software ID FIGURE 18: Software Product Command Flowcharts ©2010 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Software Product ID Exit & Reset Command Sequence Load data: AAH Load data: F0H Address: 5555H Address: XXH ...

Page 19

... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Chip-Erase Command Sequence Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: 80H Address: 5555H Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: 10H Address: 5555H ...

Page 20

... Data Sheet PRODUCT ORDERING INFORMATION SST 39 SF 010A - XXXX - XX ©2010 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 - XXX X Environmental Attribute Package Modifier Package Type Temperature Range Minimum Endurance Read Access Speed Version Device Density Voltage Product Series ...

Page 21

... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Valid combinations for SST39SF010A SST39SF010A-55-4C-NHE SST39SF010A-55-4C-WHE SST39SF010A-70-4C-NHE SST39SF010A-70-4C-WHE SST39SF010A-55-4I-NHE SST39SF010A-55-4I-WHE SST39SF010A-70-4I-NHE SST39SF010A-70-4I-WHE Valid combinations for SST39SF020A SST39SF020A-55-4C-NHE SST39SF020A-55-4C-WHE SST39SF020A-70-4C-NHE SST39SF020A-70-4C-WHE SST39SF020A-55-4I-NHE SST39SF020A-55-5I-WHE SST39SF020A-70-4I-NHE SST39SF020A-70-4I-WHE Valid combinations for SST39SF040 SST39SF040-55-4C-NHE SST39SF040-55-4C-WHE SST39SF040-70-4C-NHE SST39SF040-70-4C-WHE SST39SF040-55-4I-NHE ...

Page 22

... Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 4. Coplanarity: 4 mils. FIGURE 20: 32-lead Plastic Lead Chip Carrier (PLCC) SST Package Code: NH ©2010 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 SIDE VIEW .112 .106 .029 .040 .020 R. x 30˚ ...

Page 23

... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Pin # 1 Identifier 12.50 12.30 0.70 0.50 14.20 13.80 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0 Maximum allowable mold flash is 0. the package ends, and 0.25 mm between leads. ...

Page 24

... All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. FIGURE 22: 32-pin Plastic Dual In-line Pins (PDIP) SST Package Code: PH ©2010 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 1.655 1.645 .200 .170 .150 ...

Page 25

... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 TABLE 11: Revision History Number 02 • 2002 Data Book 03 • Changes to Table 5 on page 8 – Added footnote for MPF power usage and Typical conditions – Clarified the Test Conditions for Power Supply Current and Read parameters – ...

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