CS8415A-CSZ Cirrus Logic Inc, CS8415A-CSZ Datasheet - Page 30

• Manufacturer Part Number: CS8415A-CSZ
• Description: IC,Digital Audio Receiver,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS8415A-CSZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

30
9. PIN DESCRIPTION - SOFTWARE MODE
SDA/CDOUT
AD0/CS
EMPH
RXP0
RXN0
RXP1
RXP2
RXP4
RXP6
VA+
Pin Name
RXP3
RXP5
12
13
14
15
25
26
#
1
2
3
4
5
6
Serial Control Data I/O (I²C) / Data Out (SPI) (Input/Output) - In I²C mode, SDA is the control I/O data
line. SDA is open drain and requires an external pull-up resistor to VL+. In SPI mode, CDOUT is the out-
put data from the control port interface on the CS8415A
Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - A falling edge on this pin puts the
CS8415A into SPI control port mode. With no falling edge, the CS8415A defaults to I²C mode. In I²C
mode, AD0 is a chip address pin. In SPI mode, CS is used to enable the control port interface on the
CS8415A
Pre-Emphasis (Output) - EMPH
pre-emphasis.
emphasis other than 50/15 ms. This is also a start-up option pin, and requires a 47 kΩ resistor to either
VL+ or DGND, which determines the AD2 address bit for the control port in I²C mode
AES3/SPDIF Receiver Port (Input) - Differential line receiver inputs carrying AES3 data. RXP0 may be
used as a single-ended input as part of 7:1 S/PDIF Input MUX. If RXP0 is used in MUX, RXN0 must be
ac coupled to ground.
Additional AES3/SPDIF Receiver Port (Input) - Single-ended receiver inputs carrying AES3 or S/PDIF
digital data. These inputs, along with RXP0, comprise the 7:1 S/PDIF Input Multiplexer and select line
control is accessed using the MUX2:0 bits in the Control 2 register. Please note that any unused inputs
should be tied to ground. See Appendix A for recommended input circuits.
Positive Analog Power (Input) - Positive supply for the analog section. Nominally +5.0 V. This supply
should be as quiet as possible since noise on this pin will directly affect the jitter performance of the
recovered clock
Pin Description
SDA/CDOUT
* Pins which remain the same function in all modes.
+ Pins which require a pull up or pull down resistor
AD0/CS
to select the desired startup option.
RMCK
EMPH
AGND
EMPH
RERR
RXP0
RXN0
RXP1
RXP2
RXP3
FILT
RST
VA+
is high when the Channel Status data indicates no pre-emphasis or indicates pre-
1
2
3*+
4*
5*
6*
7*
8*
9*
10*
11*
12
13
14
is low when the incoming Channel Status data indicates 50/15 ms
*24
*23
*22
*21
*18
*17
*16
28
27
26
25
20
19
15
SCL/CCLK
AD1/CDIN
RXP6
RXP5
H/S
V +
DGND
OMCK
U
INT
SDOUT
OLRCK
OSCLK
RXP4
L
CS8415A
DS470F4