DAC8420ES Analog Devices Inc, DAC8420ES Datasheet - Page 16

• Manufacturer Part Number: DAC8420ES
• Description: D/A Converter (D-A) IC
• Manufacturer: Analog Devices Inc

Specifications of DAC8420ES

• Resolution (bits): 12bit
• Digital Ic Case Style: SOIC
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +85°C
• Update Rate: 0.125MSPS
• Mounting Type: Surface Mount
• Peak Reflow Compatible (260 C): No
• Rohs Status: RoHS non-compliant
• Settling Time: 8µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 4
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 255mW
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Number Of Channels: 4
• Resolution: 12b
• Conversion Rate: 125KSPS
• Interface Type: Serial (3-Wire)
• Single Supply Voltage (typ): 5V
• Dual Supply Voltage (typ): ±5/±15V
• Power Supply Requirement: Single/Dual
• Output Type: Voltage
• Integral Nonlinearity Error: ±3LSB
• Single Supply Voltage (min): 4.75V
• Single Supply Voltage (max): 5.25V
• Dual Supply Voltage (min): ±4.75V
• Dual Supply Voltage (max): ±15.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: SOIC W
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DAC8420
VREFHI INPUT REQUIREMENTS
The DAC8420 utilizes a unique, patented DAC switch driver
circuit that compensates for different supply, reference voltage,
and digital code inputs. This ensures that all DAC ladder switches
are always biased equally, ensuring excellent linearity under all
conditions. Thus, as shown in Table 1, the VREFHI input of the
DAC8420 requires both sourcing and sinking current capabili-
ties from the reference voltage source. Many positive voltage
references are intended as current sources only and offer little
sinking capability. The user should consider references such as
the AD584, AD586, AD587, AD588, AD780, and
such an application.
REF43
for
Rev. B | Page 16 of 24
POWER-UP SEQUENCE
To prevent a CMOS latch-up condition, power up VDD, VSS,
and GND prior to any reference voltages. The ideal power-up
sequence is GND, VSS, VDD, VREFHI, VREFLO, and digital
inputs. Noncompliance with the power-up sequence over an
extended period can elevate the reference currents and eventually
damage the device. On the other hand, if the noncompliant
power-up sequence condition is as short as a few milliseconds,
the device can resume normal operation without being damaged
once VDD/VSS is powered.