DAC8420FS Analog Devices Inc, DAC8420FS Datasheet - Page 21

• Manufacturer Part Number: DAC8420FS
• Description: D/A Converter (D-A) IC
• Manufacturer: Analog Devices Inc

Specifications of DAC8420FS

• Resolution (bits): 12bit
• No. Of Pins: 16
• Peak Reflow Compatible (260 C): No
• Update Rate: 0.125MSPS
• No. Of Bits: 12 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Interface Type: Serial
• Rohs Status: RoHS non-compliant
• Settling Time: 8µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 4
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 255mW
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DAC8420 TO M68HC11 INTERFACE ASSEMBLY PROGRAM
* M68HC11 Register Definitions
PORTC EQU $1003 Port C control register
* “0,0,0,0;0,CLSEL,CLR,CS”
DDRC EQU $1007 Port C data direction
PORTD EQU $1008 Port D data register
* “0,0,LD,SCLK;SDI,0,0,0”
DDRD EQU $1009 Port D data direction
SPCR EQU $1028 SPI control register
* “SPIE,SPE,DWOM,MSTR;CPOL,CPHA,SPR1,SPR0”
SPSR EQU $1029 SPI status register
* “SPIF,WCOL,0,MODF;0,0,0,0”
SPDR EQU $102A SPI data register; Read-Buffer; Write-Shifter
*
* SDI RAM variables: SDI1 is encoded from 0 (Hex) to CF (Hex)
* To select: DAC A – Set SDI1 to $0X
* DAC requires two 8-bit loads – Address + 12 bits
SDI1 EQU $00 SDI packed byte 1 “A1,A0,0,0;MSB,DB10,DB9,DB8”
SDI2 EQU $01 SDI packed byte 2
“DB7,DB6,DB5,DB4;DB3,DB2,DB1,DB0”
* Main Program
ORG $C000 Start of user’s RAM in EVB
INIT LDS #$CFFF Top of C page RAM
* Initialize Port C Outputs
* CLSEL-Hi, CLR-Hi, CS-Hi
* To reset DAC to ZERO-SCALE, set CLSEL-Lo ($03)
* To reset DAC to MID-SCALE, set CLSEL-Hi ($07)
* Initialize Port D Outputs
* LD-Hi,SCLK-Hi,SDI-Lo
DAC B – Set SDI1 to $4X
DAC C – Set SDI1 to $8X
DAC D – Set SDI1 to $CX
SDI2 is encoded from 00 (Hex) to FF (Hex)
LDAA #$07 0,0,0,0;0,1,1,1
STAA PORTC Initialize Port C Outputs
LDAA #$07 0,0,0,0;0,1,1,1
STAA DDRC CLSEL, CLR, and CS are now enabled as outputs
LDAA #$30 0,0,1,1;0,0,0,0
STAA PORTD Initialize Port D Outputs
LDAA #$38 0,0,1,1;1,0,0,0
STAA DDRD LD,SCLK, and SDI are now enabled as outputs
Rev. B | Page 21 of 24
* Initialize SPI Interface
* Call update subroutine
* Subroutine UPDATE
UPDATE PSHX Save registers X, Y, and A
* Enter Contents of SDI1 Data Register (DAC# and 4 MSBs)
* Enter Contents of SDI2 Data Register
* Clear DAC output to zero
* Get DAC ready for data input
TFRLP LDAA 0,X Get a byte to transfer via SPI
WAIT LDAA SPSR Loop to wait for SPIF
*
* Update DAC output with contents of DAC register
LDAA #$5F
STAA SPCR SPI is Master,CPHA=1,CPOL=1,Clk rate=E/32
BSR UPDATE Xfer 2 8-bit words to DAC-8420
JMP $E000 Restart BUFFALO
PSHY
PSHA
LDAA #$80 1,0,0,0;0,0,0,0
STAA SDI1 SDI1 is set to 80 (Hex)
LDAA #$00 0,0,0,0;0,0,0,0
STAA SDI2 SDI2 is set to 00 (Hex)
LDX #SDI1 Stack pointer at 1st byte to send via SDI
LDY #$1000 Stack pointer at on-chip registers
BCLR PORTC,Y $02 Assert CLR
BSET PORTC,Y $02 Deassert CLR
BCLR PORTC,Y $01 Assert CS
STAA SPDR Write SDI data reg to start xfer
BPL WAIT SPIF is the MSB of SPSR
INX
CPX #SDI2+ 1 Are we done yet ?
BNE TFRLP If not, xfer the second byte
BCLR PORTD,Y 520 Assert LD
BSET PORTD,Y $20 Latch DAC register
BSET PORTC,Y $01 De-assert CS
PULA When done, restore registers X, Y & A
PULY
PULX
RTS
(when SPIF is set, SPSR is negated)
** Return to Main Program **
Increment counter to next byte for xfer
DAC8420