DS90CF386MTD National Semiconductor, DS90CF386MTD Datasheet - Page 11

• Manufacturer Part Number: DS90CF386MTD
• Description: Line Receiver IC
• Manufacturer: National Semiconductor

Specifications of DS90CF386MTD

• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 3.30V
• Leaded Process Compatible: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
V
GND
PLL V
PLL GND
LVDS V
LVDS GND
DS90CF386 Pin Description — 24-Bit FPD Link Receiver
DS90CF366 Pin Description — 18-Bit FPD Link Receiver
RECEIVER FAILSAFE FEATURE:
These receivers have input failsafe bias circuitry to guaran-
tee a stable receiver output for floating or terminated re-
ceiver inputs. Under these conditions receiver inputs will be
in a HIGH state. If a clock signal is present, data outputs will
all be HIGH; if the clock input is also floating/terminated, data
outputs
floating/terminated clock input will result in a LOW clock out-
put.
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
V
GND
PLL V
PLL GND
LVDS V
LVDS GND
CC
Pin Name
Pin Name
CC
CC
CC
CC
CC
will
remain
I/O
O
O
I
I
I
I
I
I
I
I
I
I
I
I/O
O
O
I
I
I
I
I
I
I
I
I
I
I
No.
in
21
3
3
1
1
1
1
4
5
1
2
1
3
the
No.
28
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines — FPLINE,
FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The falling edge acts as data strobe.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
Power supply for PLL.
Ground pin for PLL.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
4
4
1
1
1
1
4
5
1
2
1
3
last
valid
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 3 control
lines — FPLINE, FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data
Enable).
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The falling edge acts as data strobe.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
Power supply for PLL.
Ground pin for PLL.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
state.
A
11
Description
Description
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